MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 761

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

The 16-bit counter bus selector is common to all input and output functions; it connects the MDASM to
one of the four 16-bit counter buses available to that submodule instance and is controlled in software by
the 16-bit counter bus selector bits BSL0 and BSL1 in the MDASMSCR register.
17.9.3
The mode of operation of the MDASM is determined by the mode select bits MODE[0:3] in the
MDASMSCR register (see
To avoid spurious interrupts, and to make sure that the FLAG line is activated according to the newly
selected mode, the following sequence of operations should be adopted when changing mode:
17.9.3.1
The disable mode is selected by setting MODE[0:3] to 0b0000.
In this mode, all input capture and output compare functions of the MDASM are disabled and the FLAG
line is maintained inactive, but the input port signal function remains available. The associated signal
becomes a high impedance input and the input level on this signal is reflected by the state of the PIN bit
in the MDASMSCR register. All control bits remain accessible, allowing the software to prepare for future
Freescale Semiconductor
MODE[0:3]
1. Disable MDASM interrupts (by resetting the enable bit in the relevant MIRSM)
2. Change mode (via disable mode)
3. Reset the corresponding FLAG bit in the relevant MIRSM
4. Re-enable MDASM interrupts (if desired)
0000
0001
0010
0011
0100
0101
1xxx
MDASM Modes of Operation
OPWM
OCAB
IPWM
Disable (DIS) Mode
Mode
OCB
IPM
DIS
IC
When changing between output modes, it is not necessary to follow this
procedure, as in these modes the FLAG bit merely indicates to the software
that the compare value can be updated. However changing modes without
passing via the disable mode does not guarantee the subsequent
functionality.
Disabled — Input signal is high impedance; PIN gives state of the input signal.
Input pulse width measurement — Capture on the leading edge and the trailing edge of an input pulse.
Input period measurement — Capture two consecutive rising/falling edges.
Input capture — Capture when the designated edge is detected.
Output compare, flag line activated on B compare — Generate leading and trailing edges of an output
pulse.
Output compare, flag line activated on A and B compare — Generate leading and trailing edges of an
output pulse.
Output pulse width modulation — Generate continuous PWM output with 7, 9, 11, 12, 13, 14, 15 or 16
bits of resolution.
Table
Table 17-16. MDASM Modes of Operation
MPC561/MPC563 Reference Manual, Rev. 1.2
17-16).
NOTE
Description of Mode
Modular Input/Output Subsystem (MIOS14)
17-29