MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 957

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

SRESET
SRESET
23.6.4
This register enables selectively masking the events that may cause the processor to enter into debug mode.
Freescale Semiconductor
Field
Field
Addr
22:27
Bits
28
29
30
31
MSB
—
16
—
0
0
RSTE CHSTPE
SEEE
Debug Enable Register (DER)
17
0
1
Name
EBRK
LBRK
IBRK
DPI
—
Bits
18
—
0:1
1
2
1
2
3
Reserved
L-bus breakpoint exception bit. This bit is set as a result of the assertion of a load/store
breakpoint. Results in debug mode entry if debug mode is enabled and the corresponding enable
bit is set.
I-bus breakpoint exception bit. This bit is set as a result of the assertion of an Instruction
breakpoint. Results in debug mode entry if debug mode is enabled and the corresponding enable
bit is set.
External breakpoint exception bit. Set when an external breakpoint is asserted (by an on-chip
IMB or L-bus module, or by an external device or development system through the development
port). This bit is set as a result of the assertion of an external breakpoint. Results in debug mode
entry if debug mode is enabled and the corresponding enable bit is set.
Development port interrupt bit. Set by the development port as a result of a debug station
non-maskable request or when debug mode is entered immediately out of reset.
ITLBERE
MCEE
CHSTPE
19
3
0
MCEE
Name
RSTE
—
Table 23-18. ECR Bit Descriptions (continued)
Figure 23-17. Debug Enable Register (DER)
MPC561/MPC563 Reference Manual, Rev. 1.2
20
—
4
Table 23-19. DER Bit Descriptions
Reserved
Reset enable
0 Debug entry is disabled (reset value)
1 Debug entry is enabled
Checkstop enable bit
0 Debug mode entry disabled
1 Debug mode entry enabled (reset value)
Machine check exception enable bit
0 Debug mode entry disabled (reset value)
1 Debug mode entry enabled
0000_0000_0000
DTLBERE
—
21
5
EXTIE ALEE PREE FPUVEE DECEE
22
6
SPR 149
23
7
0000_0000_0
Description
Description
24
8
—
25
9
10
26
11
27
—
LBRKE IBRKE EBRKE DPIE
12
28
1
Development Support
SYSEE
13
29
0
1
TRE
14
30
1
1
23-43
FPASE
LSB
15
31
0
1