MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 923

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

23.2.1
This section describes the internal breakpoints and watchpoints support of the RCPU. For information on
external breakpoints support refer to
Internal breakpoint and watchpoint support is based on eight comparators comparing information on
instruction and load/store cycles, two counters, and two AND-OR logic structures. The comparators
perform compare on the Instruction address (I-address), on the load/store address (L-address) and on the
load/store data (L-data).
The comparators are able to detect the following conditions: equal, not equal, greater than, less than
(greater than or equal and less than or equal are easily obtained from these four conditions; for more
information refer to
structures “in range” and “out of range” detections (on address and on data) are supported. Using the
counters, it is possible to program a breakpoint to be recognized after an event was detected a predefined
number of times.
The L-data comparators can operate on fix point data of load or store. When operating on fix point data
the L-data comparators are able to perform compare on bytes, half-words and words and can treat numbers
either as signed or as unsigned values.
Freescale Semiconductor
Internal
Watchpoints
Logic
Development
Port
Development
System OR
External
Peripherals
LCTRL2
MSR
X
X
Internal Watchpoints and Breakpoints
(Non-masked Control Bit)
Non-maskable Breakpoint
MSR[RI]
Maskable Breakpoint
Development Port Trap Enable Bits
Software trap Enable Bits
bit wise AND
bit wise OR
Watchpoints
Section 23.2.1.6, “Generating Six Compare
Figure 23-1. Watchpoint and Breakpoint Support in the CPU
Internal
Peripherals
MPC561/MPC563 Reference Manual, Rev. 1.2
Section 23.3, “Development System
X
Counters
Types”). Using the AND-OR logic
X
Interface.”
To Watchpoint
Pins
Breakpoint
to CPU
Development Support
23-9