MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 295

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

7.5
7.5.1
When a hard reset event occurs, the MPC561/MPC563 reconfigures its hardware system as well as the
development port configuration. The logical value of the bits that determine its initial mode of operation,
are sampled from the following:
If at the sampling time RSTCONF is asserted, then the configuration is sampled from the external data
bus. If RSTCONF is negated and a valid NVM value exists (UC3FCFIG[HC]=0), then the configuration
is sampled from the NVM register in the UC3F module. If RSTCONF is negated and no valid NVM value
exists (UC3FCFIG[HC]=1), then the configuration word is sampled from the internal default (all zeros).
HC will be “1” if the internal Flash is erased.
If the PRDS control bit in the PDMCR register is cleared and HRESET and RSTCONF are asserted, the
MPC561/MPC563 pulls the data bus low with a weak resistor. The user can overwrite this default by
driving the appropriate bit high. See
Freescale Semiconductor
•
•
•
The external data bus pins DATA[0:31]
An internal default constant (0x0000 0000)
An internal NVM register value (UC3FCFIG). Available on the MPC563/MPC564 only.
Reset Configuration
RSTCONF
Hard Reset Configuration
0
1
1
Has Configuration (HC)
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 7-4. Reset Configuration Options
x
0
1
Figure 7-2
Table 7-4
for the basic reset configuration scheme.
DATA[0:31] pins
NVM Flash EEPROM register (UC3FCFIG)
Internal data word default (0x0000 0000)
summarizes the reset configuration options.
Internal Configuration Word
Reset
7-7