MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 834

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Time Processor Unit 3
time (latency) determines TPU3 performance in a given application. Latency can be closely estimated. For
more information, refer to the TPU Reference Manual (TPURM/AD).
19.3.2
Most timer systems are limited by the fixed number of functions assigned to each pin. All TPU3 channels
contain identical hardware and are functionally equivalent in operation, so that any channel can be
configured to perform any time function. Any function can operate on the calling channel, and, under
program control, on another channel determined by the program or by a parameter. The user controls the
combination of time functions.
19.3.3
The autonomy of the TPU3 is enhanced by the ability of a channel to affect the operation of one or more
other channels without CPU intervention. Interchannel communication can be accomplished by issuing a
link service request to another channel, by controlling another channel directly, or by accessing the
parameter RAM of another channel.
19.3.4
The TPU3 provides a programmable service priority level to each channel. Three priority levels are
available. When more than one channel of a given priority requests service at the same time, arbitration is
accomplished according to channel number. To prevent a single high-priority channel from permanently
blocking other functions, other service requests of the same priority are performed in channel order after
the lowest-numbered, highest-priority channel is serviced (i.e. round-robin).
19.3.5
For data to be coherent, all available portions of the data must be identical in age, or must be logically
related. As an example, consider a 32-bit counter value that is read and written as two 16-bit words. The
32-bit value is read-coherent only if both 16-bit portions are updated at the same time, and write-coherent
only if both portions take effect at the same time. Parameter RAM hardware supports coherent access of
two adjacent 16-bit parameters. The host CPU must use a long-word operation to guarantee coherency.
19.3.6
Although factory-programmed time functions can perform a wide variety of control tasks, they may not
be ideal for all applications. The TPU3 provides emulation capability that allows the development of new
time functions. Emulation mode is entered by setting the EMU bit in TPUMCR. In emulation mode, an
auxiliary bus connection is made between the DPTRAM and the TPU3, and access to DPTRAM via the
intermodule bus is disabled. A 9-bit address bus, a 32-bit data bus, and control lines transfer information
between the modules. To ensure exact emulation, DPTRAM module access timing remains consistent with
access timing of the TPU microcode ROM control store.
To support changing TPU application requirements, Freescale has established a TPU function library. The
function library is a collection of TPU functions written for easy assembly in combination with each other
19-4
Channel Orthogonality
Interchannel Communication
Programmable Channel Service Priority
Coherency
Emulation Support
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor