MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 126

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

[PCS6EN]
PDMCR2
Signal Descriptions
2.5
On the MPC561/MPC563, the JTAG, BDM, and READI (Nexus interface) signals are all shared. Only one
set of signals can be active at a time.
2-28
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
[PCS7EN]
PDMCR2
MPC561/MPC563 Development Support Signal Sharing
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
TDO/DSDO/MDO0
1
TCK/DSCK/MCKI
Only one set of signals are enabled at a time.
TDI/DSDI/MDI0
JCOMP/RSTI
TMS/EVTI
PULL_
Signal
Table 2-12. MPC561/MPC563 Development Support Shared Signals
DIS5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
[SH_ET1]
SHORT_
REG
Table 2-11. Enhanced PCS 6 & 7 Pad Function
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MPC561/MPC563 Reference Manual, Rev. 1.2
[SH_ET2]
SHORT_
Table 2-12
Direction
Output
REG
Input
Input
Input
Input
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
ETRIG1/PCS6
PAD Function
shows the shared functions in the different modes.
ETRIG1
ETRIG1
ETRIG1
ETRIG1
ETRIG1
ETRIG1
ETRIG1
ETRIG1
PCS6
PCS6
PCS6
PCS6
PCS6
PCS6
PCS6
PCS6
JCOMP
JTAG
TDO
TMS
TCK
TDI
ETRIG2/PCS7
PAD Function
ETRIG2
ETRIG2
ETRIG2
ETRIG2
ETRIG2
ETRIG2
ETRIG2
ETRIG2
PCS7
PCS7
PCS7
PCS7
PCS7
PCS7
PCS7
PCS7
DSDO
DSCK
BDM
DSDI
—
0
Disabled
Disabled A_TPUCH15 B_TPUCH15
Disabled
Disabled A_TPUCH15 B_TPUCH15
Disabled
Disabled A_TPUCH15 B_TPUCH15
Disabled
Disabled A_TPUCH15 B_TPUCH15
Enabled
Enabled A_TPUCH15 B_TPUCH15
Enabled
Enabled A_TPUCH15 B_TPUCH15
Enabled
Enabled A_TPUCH15 B_TPUCH15
Enabled
Enabled A_TPUCH15 B_TPUCH15
Pull-up
Pad
connection
READI
MDO0
MCKI
Freescale Semiconductor
MDI0
RSTI
EVTI
ETRIG 1
internal
ETRIG1
ETRIG1
ETRIG1
ETRIG1
PCS6
PCS6
PCS6
PCS6
connection
ETRIG2
internal
ETRIG2
ETRIG2
ETRIG2
ETRIG2
PCS7
PCS7
PCS7
PCS7