MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 158

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Central Processing Unit
A listing of FPSCR bit settings is shown in
3-14
Bits
Reset
Reset
10
11
0
1
2
3
4
5
6
7
8
9
Field FX FEX VX
Field
MSB
VXSNAN
16
0
VXZDZ
VXIMZ
Name
VXIDI
VXISI
FEX
OX
UX
FX
VX
ZX
XX
FPRF[1:4]
17
1
Figure 3-6. Floating-Point Status and Control Register (FPSCR)
18
Floating-point exception summary. Every floating-point instruction implicitly
sets FPSCR[FX] if that instruction causes any of the floating-point exception
bits in the FPSCR to change from 0 to 1. The mcrfs instruction implicitly clears
FPSCR[FX] if the FPSCR field containing FPSCR[FX] has been copied. The
mtfsf, mtfsfi, mtfsb0, and mtfsb1 instructions can set or clear FPSCR[FX]
explicitly.
Floating-point enabled exception summary. This bit signals the occurrence of
any of the enabled exception conditions. It is the logical OR of all the
floating-point exception bits masked with their respective enable bits. The
mcrfs instruction implicitly clears FPSCR[FEX] if the result of the logical OR
described above becomes zero. The mtfsf, mtfsfi, mtfsb0, and mtfsb1
instructions cannot set or clear FPSCR[FEX] explicitly.
Floating-point invalid operation exception summary. This bit signals the
occurrence of any invalid operation exception. It is the logical OR of all of the
invalid operation exceptions. The mcrfs instruction implicitly clears
FPSCR[VX] if the result of the logical OR described above becomes zero. The
mtfsf, mtfsfi, mtfsb0, and mtfsb1 instructions cannot set or clear FPSCR[VX]
explicitly.
Floating-point overflow exception.
Floating-point underflow exception.
Floating-point zero divide exception.
Floating-point inexact exception.
Floating-point invalid operation exception for SNaN.
Floating-point invalid operation exception for ∞ - ∞.
Floating-point invalid operation exception for ∞/∞.
Floating-point invalid operation exception for 0/0.
Floating-point invalid operation exception for ∞ x 0.
2
OX
19
3
UX
20
0
4
MPC561/MPC563 Reference Manual, Rev. 1.2
SOFT
Table 3-5. FPSCR Bit Descriptions
ZX
VX
21
5
SQRT
XX
VX
22
6
Table
VXCVI
VXSN
AN
23
3-5.
7
Unchanged
Unchanged
VXISI VXIDI VXZDZ VXIMZ VXVC FR
VE
24
8
Description
OE
25
9
UE
10
26
ZE
11
27
XE
12
28
Freescale Semiconductor
NI
13
29
Not sticky
Not sticky
Sticky bit
Sticky bit
Sticky bit
Sticky bit
Sticky bit
Sticky bit
Sticky bit
Sticky bit
Sticky bit
Sticky bit
14
30
FI FPRF0
RN
LSB
15
31