MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 493

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

A scan sequence may be initiated by the following:
The software also specifies whether the QADC64E is to perform a single pass through the queue or is to
scan continuously. When a single-scan mode is selected, the software selects the queue operating mode
and sets the single-scan enable bit. When a continuous-scan mode is selected, the queue remains active in
the selected queue operating mode after the QADC64E completes each queue scan sequence.
During queue execution, the QADC64E reads each CCW from the active queue and executes conversions
in three stages:
When the pause bit is set in the current CCW, the QADC64E stops execution of the queue until a new
trigger event occurs. The pause status flag bit is set, which may cause an interrupt to notify the software
that the queue has reached the pause state. After the trigger event occurs, the paused state ends and the
QADC64E continues to execute each CCW in the queue until another pause is encountered or the end of
the queue is detected.
The following indicate the end-of-queue condition:
When any of the end-of-queue conditions is recognized, a queue completion flag is set, and if enabled, an
interrupt is issued to the software.
The following situations prematurely terminate queue execution:
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A software command
Expiration of the periodic/interval timer
External trigger signal
External gated signal (queue 1 only)
Initial sample - During initial sample, a buffered version of the selected input channel is connected
to the sample capacitor at the input of the sample buffer amplifier.
Final sample - During the final sample period, the sample buffer amplifier is bypassed, and the
multiplexer input charges the sample capacitor directly. Each CCW specifies a final input sample
time of 2, 4, 8, or 16 cycles.
Resolution - When an analog-to-digital conversion is complete, the result is written to the
corresponding location in the result word table. The QADC64E continues to sequentially execute
each CCW in the queue until the end of the queue is detected or a pause bit is found in a CCW.
The CCW channel field is programmed with 63 (0x3F) to specify the end of the queue
The end-of-queue 1 is implied by the beginning of queue 2, which is specified in the BQ2 field in
QACR2
The physical end of the queue RAM space defines the end of either queue
Because queue 1 is higher in priority than queue 2, when a trigger event occurs on queue 1 during
queue 2 execution, the execution of queue 2 is suspended by aborting the execution of the CCW in
progress, and the queue 1 execution begins. When queue 1 execution is completed, queue 2
conversions restart with the first CCW entry in queue 2 or the first CCW of the queue 2 sub-queue
being executed when queue 2 was suspended. Alternately, conversions can restart with the aborted
queue 2 CCW entry. The RESUME bit in QACR2 allows the software to select where queue 2
begins after suspension. By choosing to re-execute all of the suspended queue 2 queue and
MPC561/MPC563 Reference Manual, Rev. 1.2
QADC64E Legacy Mode Operation
13-29