MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 28

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

21.3.8
21.3.8.1
21.3.8.2
21.3.8.3
21.3.9
21.3.10
21.3.11
21.3.11.1
21.3.11.2
21.3.11.3
21.3.11.4
21.3.12
22.1
22.2
22.3
22.4
22.4.1
22.4.2
22.4.2.1
22.4.3
22.4.4
22.4.5
22.4.6
22.4.6.1
22.4.6.2
22.4.6.3
22.4.6.4
22.5
22.5.1
22.5.2
22.5.3
22.5.4
Freescale Semiconductor
Paragraph
Number
Features ......................................................................................................................... 22-1
CALRAM Block Diagram ............................................................................................ 22-2
CALRAM Memory Map .............................................................................................. 22-2
Modes of Operation ...................................................................................................... 22-4
Programming Model ................................................................................................... 22-12
Erasing .................................................................................................................... 21-25
Stop Operation ........................................................................................................ 21-28
Disabled .................................................................................................................. 21-29
Censored Accesses and Non-Censored Accesses ................................................... 21-29
Background Debug Mode or Freeze Operation ...................................................... 21-34
Reset .......................................................................................................................... 22-5
One-Cycle Mode ....................................................................................................... 22-5
Two-Cycle Mode ...................................................................................................... 22-5
Stop Operation .......................................................................................................... 22-6
CALRAM Module Configuration Register (CRAMMCR) .................................... 22-13
CALRAM Region Base Address Registers (CRAM_RBAx) ................................ 22-15
CALRAM Overlay Configuration Register (CRAM_OVLCR) ............................. 22-17
CALRAM Ownership Trace Register (CRAM_OTR) ........................................... 22-17
Standby Operation/Keep-Alive Power .................................................................... 22-5
Overlay Mode Operation ......................................................................................... 22-6
Erase Sequence ................................................................................................... 21-26
Erasing Shadow Information Words .................................................................. 21-28
Erase Suspend ..................................................................................................... 21-28
Setting and Clearing Censor ............................................................................... 21-31
Setting Censor ..................................................................................................... 21-32
Clearing Censor .................................................................................................. 21-32
Switching The UC3F EEPROM Censorship ...................................................... 21-33
CALRAM Access/Privilege Violations ................................................................ 22-5
Overlay Mode Configuration ................................................................................ 22-6
Priority of Overlay Regions ................................................................................ 22-11
Normal (Non-Overlay) Access to Overlay Regions ........................................... 22-12
Calibration Write Cycle Flow ............................................................................. 22-12
MPC561/MPC563 Reference Manual, Rev. 1.2
CALRAM Operation
Contents
Chapter 22
Title
Number
Page
xxviii