MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 663

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

15.7.1
The SCI programming model includes the QSMCM global and pin control registers and the DSCI
registers.
The DSCI registers, listed in
data registers. All registers may be read or written at any time by the CPU. Rewriting the same value to
any DSCI register does not disrupt operation; however, writing a different value into a DSCI register when
the DSCI is running may disrupt operation. To change register values, the receiver and transmitter should
be disabled with the transmitter allowed to finish first. The status flags in register SCxSR can be cleared
at any time.
Freescale Semiconductor
SCI Registers
(non-queue mode only
0x30 500A
0x30 500C
0x30 500E
0x30 502A
0x30 5008
0x30 5020
0x30 5022
0x30 5024
0x30 5026
0x30 5028
Address
Table
MPC561/MPC563 Reference Manual, Rev. 1.2
15-23, consist of five control registers, three status registers, and 34
Table 15-23. SCI Registers
QSCI1CR
QSCI1SR
SCC1R0
SCC1R1
SCC2R0
SCC2R1
SC1DR
SC2DR
SC1SR
SC2SR
Name
SCI1 Control Register 0
See <XrefBlue>Table 15-24 for bit
descriptions.
SCI1 Control Register 1
See <XrefBlue>Table 15-25 for bit
descriptions.
SCI1 Status Register
See <XrefBlue>Table 15-26 for bit
descriptions.
SCI1 Data Register
Transmit Data Register (TDR1)*
Receive Data Register (RDR1)*
See <XrefBlue>Table 15-27 for bit
descriptions.
SCI2 Control Register 0
SCI2 Control Register 1
SCI2 Status Register
SCI2 Data Register
Transmit Data Register (TDR2)*
Receive Data Register (RDR2)*
QSCI1 Control Register
Interrupts, wrap, queue size and enables
for receive and transmit, QTPNT.
See <XrefBlue>Table 15-32 for bit
descriptions.
QSCI1 Status Register
OverRun error flag, queue status flags,
QRPNT, and QPEND.
See <XrefBlue>Table 15-33 for bit
descriptions.
Usage
Queued Serial Multi-Channel Module
15-45