MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 196

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Central Processing Unit
When a program exception is taken, instruction execution resumes at offset 0x0700 from the physical base
address indicated by MSR[IP].
3.15.4.8
A floating-point unavailable exception occurs when no higher priority exception exists, an attempt is made
to execute a floating-point instruction (including floating-point load, store, and move instructions), and the
floating-point available bit in the MSR is disabled, (MSR[FP] = 0).
3-52
1
2
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain a
compressed address.
Only one of bits 11, 13, and 14 can be set.
Machine State Register (MSR)
Floating-Point Unavailable Exception (0x0800)
Table 3-29. Register Settings following a Floating-Point Unavailable Exception
Register
Register
Table 3-28. Register Settings following Program Exception
1
2
1
MPC561/MPC563 Reference Manual, Rev. 1.2
DCMPEN
[16:31]
[16:31]
[0:10]
Other
[0:15]
Bits
Bits
ME
LE
All
11
12
13
14
15
All
IP
Contains the effective address of the excepting instruction
cleared.
cleared.
causing the exception, and set if SRR0 contains the address of
a subsequent instruction.
Loaded from bits [16:31] of MSR. In the current
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI].
No change
Set to value of ILE bit prior to the exception
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Set to the effective address of the instruction that caused the
exception.
Loaded from MSR[16:31]
Cleared to 0
Set for a floating-point enabled program exception; otherwise
Cleared to 0.
Set for a privileged instruction program exception; otherwise
Set for a trap program exception; otherwise cleared.
Cleared to 0 if SRR0 contains the address of the instruction
No change
Cleared to 0
Cleared to 0
Setting Description
Setting Description
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