MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 117

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Freescale Semiconductor
MPIO32B12 / C_CNTX0
MPIO32B13 / PPM_TCLK
MPIO32B14 / PPM_RX0
MPIO32B15 / PPM_TX0
A_TPUCH[0:15]
A_T2CLK / PCS5
B_TPUCH[0:15]
B_T2CLK / PCS4
NVDDL
QVDDL
VDDH
VDD
KAPWR
Signal Name
6
Table 2-1. MPC561/MPC563 Signal Descriptions (continued)
Signals
No. of
16
16
1
1
1
1
1
1
1
1
1
1
1
MPC561/MPC563 Reference Manual, Rev. 1.2
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
I
I
I
I
I
I
MPIO32B12
MPIO32B13
MPIO32B14
MPIO32B15
A_TPUCH[0:15] Provides TPU module A with 16 input/output programmable
A_T2CLK
B_TPUCH[0:15] Provides TPU module B with 16 input/output programmable
B_T2CLK
NVDDL
QVDDL
VDDH
VDD
KAPWR
Function after
Reset
Global Power
1
TPU
MIOS14 GPIO 12. This function allows the signals to be
used as general-purpose inputs/outputs.
TouCAN_C Transmit Data. This is the serial data output
signal for the TouCAN_C module.
MIOS14 GPIO 13. This function allows the signals to be
used as general-purpose inputs/outputs.
PPM_TCLK. PPM bus clock
MIOS14 GPIO 14. This function allows the signals to be
used as general-purpose inputs/outputs.
PPM_RX0. Receive data to the PPM channel number 0.
MIOS14 GPIO 15. This function allows the signals to be
used as general-purpose inputs/outputs.
PPM_TX0. Transmit data from PPM channel number 0.
timed events.
This signal is used to clock or gate the timer count register
2 (TCR2) within the TPU module A. This signal is an
output-only in special test mode.
PCS5. This signal provides QSPI peripheral chip select
when the enhanced PCS mode is selected.
timed events.
This signal is used to clock or gate the timer count register
2 (TCR2) within the TPU module B. This signal is an
output-only in special test mode.
PCS4. This signal provides QSPI peripheral chip select
when the enhanced PCS mode is selected.
NVDDL. Noisy 2.6-V voltage supply input. This signal
supplies the final output stage of the 2.6-V pad output
drivers. The NVDDL and QVDDL supplies should be
connected to the same power supply in a user's system.
QVDDL. Quiet 2.6-V voltage supply input. This signal
supplies all pad logic and pre-driver circuitry, except for the
final output stage of the 2.6-V pad output drivers.
The NVDDL and QVDDL supplies should be connected to
the same power supply in a user's system.
VDDH. 5-V voltage supply input.
VDD. 2.6-V voltage supply input for internal logic.
Keep-Alive Power. 2.6-V voltage supply input for the
oscillator and keep-alive registers.
Description
Signal Descriptions
2-19