MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 494

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

QADC64E Legacy Mode Operation
13-30
Reset
•
•
•
•
Field
Addr
Bits
0:5
6
7
sub-queue CCWs, all of the samples are guaranteed to have been taken during the same scan pass.
However, a high trigger event rate for queue 1 can prohibit the completion of queue 2. If this
occurs, the software may choose to begin execution of queue 2 with the aborted CCW entry.
Software can change the queue operating mode to disabled mode. Any conversion in progress for
that queue is aborted. Putting a queue into the disabled mode does not power down the converter.
Software can change the queue operating mode to another valid mode. Any conversion in progress
for that queue is aborted. The queue restarts at the beginning of the queue, once an appropriate
trigger event occurs.
For low power operation, software can set the stop mode bit to prepare the module for a loss of
clocks. The QADC64E aborts any conversion in progress when the stop mode is entered.
When the freeze enable bit is set by software and the IMB3 internal FREEZE line is asserted, the
QADC64E freezes at the end of the conversion in progress. When internal FREEZE is negated, the
QADC64E resumes queue execution beginning with the next CCW entry. Refer to
“Configuration and Control Using the IMB3
MSB
0
Name
BYP
—
P
1
Reserved
Pause. The pause bit allows the creation of sub-queues within queue 1 and queue 2. The
QADC64E performs the conversion specified by the CCW with the pause bit set, and then the
queue enters the pause state. Another trigger event causes execution to continue from the pause
to the next CCW.
0 Do not enter the pause state after execution of the current CCW.
1 Enter the pause state after execution of the current CCW.
Sample amplifier bypass. Setting BYP enables the amplifier bypass mode for a conversion, and
subsequently changes the timing. Refer to
Timing,” for more information.
0 Amplifier bypass mode disabled.
1 Amplifier bypass mode enabled.
2
Figure 13-16. Conversion Command Word Table (CCW)
—
3
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 13-18. CCW Bit Descriptions
0x30 4A00 – 0x30 4A7F, 0x30 4E00 – 0x30 4E7F
4
5
P
6
BYP
Unaffected
Interface” for more information.
7
Description
Section 13.4.1.2, “Amplifier Bypass Mode Conversion
8
IST
9
10
11
CHAN[5:0]
12
Freescale Semiconductor
13
Section 13.5.7,
14
LSB
15