MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 714

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

CAN 2.0B Controller Module
While its clocks are stopped, if the TouCAN senses that any one of the aforementioned conditions is no
longer true, it restarts its clocks. The TouCAN then continues to monitor these conditions and stops or
restarts its clocks accordingly.
16.6
The TouCAN can generate one interrupt level to be passed to the CPU. This level is programmed into the
priority level bits in the interrupt configuration register (CANICR). This value determines which interrupt
signal is driven onto the bus when an interrupt is requested.
Each one of the 16 message buffers can be an interrupt source, if its corresponding IMASK bit is set. There
is no distinction between transmit and receive interrupts for a particular buffer. Each of the buffers is
assigned a bit in the IFLAG register. An IFLAG bit is set when the corresponding buffer completes a
successful transmission/reception. An IFLAG bit is cleared when the CPU reads IFLAG while the
associated bit is set, and then writes it back as zero (and no new event of the same type occurs between the
read and the write actions).
The other three interrupt sources (bus off, error and wake up) act in the same way, and have flag bits
located in the error and status register (ESTAT). The bus off and error interrupt mask bits (BOFFMSK and
ERRMSK) are located in CANCTRL0, and the wake up interrupt mask bit (WAKEMSK) is located in the
module configuration register. Refer to
these registers.
The TouCAN module is capable of generating one of the 32 possible interrupt levels on the IMB3. The 32
interrupt levels are time multiplexed on the IMB3 IRQ[0:7] lines. All interrupt sources place their asserted
level on a time multiplexed bus during four different time slots, with eight levels communicated per slot.
The ILBS[0:1] signals indicate which group of eight are being driven on the interrupt request lines.
The level that the TouCAN will drive onto internal IRQ[7:0] signals is programmed in the three Interrupt
Request Level (IRL) bits located in the interrupt configuration register. The two ILBS bits in the ICR
register determine on which slot the TouCAN should drive its interrupt signal. Under the control of ILBS,
each interrupt request level is driven during the time multiplexed bus during one of four different time
slots, with eight levels communicated per time slot. No hardware priority is assigned to interrupts.
Furthermore, if more than one source on a module requests an interrupt at the same level, the system
software must assign a priority to each source requesting at that level.
levels on IRQ with ILBS.
16-20
•
The TouCAN is not in debug mode, low-power stop mode, or the bus off state
Interrupts
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 16-9. Interrupt Levels
Section 16.7, “Programming
ILBS[0:1]
00
01
10
11
Levels
16:23
24:31
8:15
0:7
Model,” for more information on
Figure 16-7
displays the interrupt
Freescale Semiconductor