MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 623

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

The supervisor-only data space segment contains the QSMCM global registers. These registers define
parameters needed by the QSMCM to integrate with the MCU. Access to these registers is permitted only
when the CPU is operating in supervisor mode.
Assignable data space can be either restricted to supervisor-only access or unrestricted to both supervisor
and user accesses. The supervisor (SUPV) bit in the QSMCM module configuration register
(QSMCMMCR) designates the assignable data space as either supervisor or unrestricted. If SUPV is set,
then the space is designated as supervisor-only space. Access is then permitted only when the CPU is
operating in supervisor mode. If SUPV is clear, both user and supervisor accesses are permitted. To clear
SUPV, the CPU must be in supervisor mode.
The QSMCM assignable data space segment contains the control and status registers for the QSPI and SCI
submodules, as well as the QSPI RAM. All registers and RAM can be accessed on byte (8-bits), half-word
(16-bits), and word (32-bit) boundaries. Word accesses require two consecutive IMB3 bus cycles.
Freescale Semiconductor
1
2
3
Access
S = Supervisor access only
S/U = Supervisor access only or unrestricted user access (assignable data space).
8-bit registers, such as SPCR3 and SPSR, are on 8-bit boundaries. 16-bit registers such as SPCR0 are on 16-bit
boundaries.
Note that QRAM offsets have been changed from the original (modular family) QSMCM.
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
1
0x30 502C –
0x30 504C –
0x30 506C –
0x30 51C0 –
0x30 5140 –
0x30 5180 –
0x30 513F
0x30 51DF
0x30 502A
0x30 504A
0x30 506A
0x30 51BF
0x30 5020
0x30 5022
0x30 5024
0x30 5026
0x30 5028
0x30 517F
Address
3
MSB
0
Table 15-1. QSMCM Register Map (continued)
2
MPC561/MPC563 Reference Manual, Rev. 1.2
See <XrefBlue>Table 15-32 for bit descriptions.
See <XrefBlue>Table 15-33 for bit descriptions.
QSCI1 Control Register (QSCI1CR)
SCI2 Control Register 0 (SCC2R0)
SCI2 Control Register 1 (SCC2R1)
QSCI1 Status Register (QSCI1SR)
Transmit Queue Locations (SCTQ)
Receive Queue Locations (SCRQ)
Transmit Data RAM (TRAN.RAM)
Receive Data RAM (REC.RAM)
SCI2 Status Register (SC2SR)
Command RAM (COMD.RAM)
SCI2 Data Register (SC2DR)
Reserved
Queued Serial Multi-Channel Module
LSB
15
15-5