MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 441

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

11.5.1
Data memory protection is assigned on a regional basis. Default manipulation of the DMPU is done on a
global region. The DMPU has control registers that contain the following information: region protection
on/off, region base address, region size, and the region’s access permissions. Each region’s protection
attributes can be turned on or off by configuring the global region attribute register’s enable attribute bit
(L2U_GRA[ENRx]).
During each load or store access from the RCPU to the U-bus, the address is compared to the value in the
region base address register of each enabled region. Any access that matches the specific region within its
appropriate size, as defined by the region attribute register’s region size field (L2U_RAx[RS]), sets a
match indication.
When more than one match indication occurs, the effective region is the region with the highest priority.
Priority is determined by region number; highest priority corresponds to the lowest region number, e.g.
region 0 is highest priority, while region 3 is lowest.
When no match occurs, the effective region is the global region, which has the lowest priority.
The region attribute register also contains the region’s protection fields. The protection field (PP) of the
effective region is compared to the access attributes. If the attributes match, the access is permitted. When
the access is permitted, a U-bus access may be generated according to the specific attribute of the effective
region.
Freescale Semiconductor
Region0 Address and size
Region2 Address and size
Region3 Address and size
Region1 Address and size
Functional Description
Address
Figure 11-2. DMPU Basic Functional Diagram
MPC561/MPC563 Reference Manual, Rev. 1.2
Select
Match
Region Protection/Attribute
Region0 protection/attribute
Region2 protection/attribute
Region1 protection/attribute
Region3 protection/attribute
Global protection/attribute
MSR[DR]
Granted
Access
Access Attribute
L-Bus to U-Bus Interface (L2U)
Error Interrupts
Exception
Specific
to Core
Logic
11-5