MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 839

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Freescale Semiconductor
0x30 440E(TPU_B))
0x30 441A(TPU_B))
0x30 441E(TPU_B))
0x30 400A(TPU_A)
0x30 440A(TPU_B)
0x30 400C(TPU_A)
0x30 440C(TPU_B)
0x30 400E(TPU_A)
0x30 401A(TPU_A)
0x30 401C(TPU_A)
0x30 441C(TPU_B)
0x30 401E(TPU_A)
0x30 402A(TPU_A)
0x30 442A(TPU_B)
0x30 402C(TPU_A)
0x30 442C(TPU_B)
0x30 402E(TPU_A)
0x30 442E(TPU_B)
0x30 4008(TPU_A)
0x30 4408(TPU_B)
0x30 4010(TPU_A)
0x30 4410(TPU_B)
0x30 4012(TPU_A)
0x30 4412(TPU_B)
0x30 4014(TPU_A)
0x30 4414(TPU_B)
0x30 4016(TPU_A)
0x30 4416(TPU_B)
0x30 4018(TPU_A)
0x30 4418(TPU_B)
0x30 4020(TPU_A)
0x30 4420(TPU_B)
0x30 4022(TPU_A)
0x30 4422(TPU_B)
0x30 4024(TPU_A)
0x30 4424(TPU_B)
0x30 4026(TPU_A)
0x30 4426(TPU_B)
0x30 4028(TPU_A)
0x30 4428(TPU_B)
Address
Table 19-6. TPU3 Register Map (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
TPU3 Interrupt Configuration Register (TICR)
See
Channel Interrupt Enable Register (CIER)
See
Channel Function Selection Register 0 (CFSR0)
See
Channel Function Selection Register 1 (CFSR1)
See
Channel Function Selection Register 2 (CFSR2)
See
Channel Function Selection Register 3 (CFSR3)
See
Host Sequence Register 0 (HSQR0)
See
Host Sequence Register 1 (HSQR1)
See
Host Service Request Register 0 (HSRR0)
See
Host Service Request Register 1 (HSRR1)
See
Channel Priority Register 0 (CPR0)
See
Channel Priority Register 1 (CPR1)
See
Channel Interrupt Status Register (CISR)
See
Link Register (LR)
Service Grant Latch Register (SGLR)
Decoded Channel Number Register (DCNR)
TPU Module Configuration Register 2 (TPUMCR2)
See
TPU Module Configuration 3 (TPUMCR3)
See
Internal Scan Data Register (ISDR)
Internal Scan Control Register (ISCR)
Table 19-10
Table 19-11
Table 19-12
Table 19-12
Table 19-12
Table 19-12
Table 19-13
Table 19-13
Table 19-14
Table 19-14
Table 19-15
Table 19-15
Table 19-17
Table 19-18
Table 19-21
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Register
Time Processor Unit 3
19-9