MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 349
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MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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9.5.2
During the data transfer phase, the data is transferred from master to slave (in write cycles) or from slave
to master (on read cycles).
During a write cycle, the master drives the data as soon as it can, but never earlier than the cycle following
the address transfer phase. The master has to take into consideration the “one dead clock cycle” switching
between drivers to avoid electrical contentions. The master can stop driving the data bus as soon as it
samples the TA line asserted on the rising edge of the CLKOUT.
During a read cycle, the master accepts the data bus contents as valid at the rising edge of the CLKOUT
in which the TA signal is sampled/asserted.
9.5.2.1
The basic read cycle begins with bus arbitration, followed by the address transfer, then the data transfer.
The handshakes illustrated in the following flow and timing figures
Figure
Freescale Semiconductor
9-6) are applicable to the fixed transaction protocol.
Single Beat Transfer
Single Beat Read Flow
4. Assert transfer start (TS)
3. Assert bus busy (BB) if no other master is driving bus
5. Drive address and attributes
2. Receive bus grant (BG) from arbiter
1. Request bus (BR)
Figure 9-4. Basic Flow Diagram of a Single Beat Read Cycle
Master
MPC561/MPC563 Reference Manual, Rev. 1.2
1. Receive address
2. Return data
3. Assert transfer acknowledge (TA)
(Figure
Slave
9-4,
Figure
External Bus Interface
9-5, and
9-9
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