MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 482

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

QADC64E Legacy Mode Operation
13-18
SRESET
Bits
3:7
0
1
2
8
Field CIE2
Addr
RESUME
MSB
0
Name
0
SSE2
CIE2
PIE2
MQ2
PIE2 SSE2
0
1
Queue 2 Completion Software Interrupt Enable. CIE2 enables an interrupt upon completion of
queue 2. The interrupt request is initiated when the conversion is complete for the CCW in
queue 2.
0 Disable the queue completion interrupt associated with queue 2
1 Enable an interrupt after the conversion of the sample requested by the last CCW in queue 2
Queue 2 Pause Software Interrupt Enable. PIE2 enables an interrupt when queue 2 enters the
pause state. The interrupt request is initiated when conversion is complete for a CCW that has
the pause bit set.
0 Disable the pause interrupt associated with queue 2
1 Enable an interrupt after the conversion of the sample requested by a CCW in queue 2 which
Queue 2 Single-Scan Enable Bit. SSE2 enables a single-scan of queue 2 to start after a trigger
event occurs. The SSE2 bit may be set to a one during the same write cycle when the MQ2 bits
are set for one of the single-scan queue operating modes. The single-scan enable bit can be
written as a one or a zero, but is always read as a zero. The SSE2 bit enables a trigger event
to initiate queue execution for any single-scan operation on queue 2. The QADC64E clears the
SSE2 bit when the single-scan is complete. Refer to
0 Trigger events are not accepted for single-scan modes
1 Accept a trigger event to start queue 2 in a single-scan mode
Queue 2 Operating Mode. The MQ2 field selects the queue operating mode for queue 2. Refer
to
0 After suspension, begin executing with the first CCW in queue 2 or the current sub-queue
1 After suspension, begin executing with the aborted CCW in queue 2
Table 13-13
has the pause bit set
0
2
Figure 13-11. Control Register 2 (QACR2)
3
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 13-12. QACR2 Bit Descriptions
for more information.
0x30 480E (QACR2_A), 0x30 4C0E (QACR2_B)
4
0_0000
MQ2
5
6
7
Description
RESUME
0
8
Table 13-13
9
10
for more information.
11
111_1111
BQ2
12
Freescale Semiconductor
13
14
LSB
15