MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 742

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Modular Input/Output Subsystem (MIOS14)
17.3.3
The read/write and control bus (RWCB) allows read and write data transfers to and from any I/O
submodule through the MBISM. It includes signals for data and addresses as well as control signals. The
control signals allow 16-bit simple synchronous single master accesses and supports fast or slow master
accesses.
17.3.4
The request bus (RQB) provides interrupt request signals along with I/O submodule identification and
priority information to the MBISM.
17.3.5
The 16-bit counter bus set (CBS) is a set of six 16-bit counter buses. The CBS makes it possible to transfer
information between submodules. Typically, counter submodules drive the CBS, while action submodules
process the data on these buses. Note, however, that some submodules are self-contained and therefore
independent of the counter bus set.
17.4
The address space of the MIOS14 consist of 4 Kbytes starting at the base address of the module
(0x306000). The overall address map organization is shown in
All MIOS14 unimplemented locations within the addressable range, return a logic 0 when accessed. In
addition, the internal TEA (transfer error acknowledge) signal is asserted.
All unused bits within MIOS14 registers return a 0 when accessed.
17.4.1
A bus error signal is generated when access to an unimplemented or reserved 16-bit register is attempted,
or when a priviledge violation occurs. A bus error is generated under any of the following conditions:
17-10
•
•
•
•
•
•
•
The read/write and control bus
The request bus
The counter bus set
Attempted access to unimplemented 16-bit registers within the decoded register block boundary.
Attempted user access to supervisor registers
Attempted access to test registers when not in test mode
Attempted write to read-only registers
MIOS14 Programming Model
Read/Write and Control Bus
Request Bus
Counter Bus Set
Bus Error Support
Some submodules do not generate interrupts and are therefore independent
of the RQB.
MPC561/MPC563 Reference Manual, Rev. 1.2
NOTE
Figure
17-2.
Freescale Semiconductor