MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 757

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Freescale Semiconductor
Bits
8:15
5:6
0
1
2
3
4
7
EDGN
EDGN
EDGP
Name
FREN
PINC
PINL
CLS
CP
—
1
1
0
0
CLS
11
10
01
00
Clock input signal status bit — This read-only status bit reflects the logic state of the clock input
signal MMCnC (MDA11, MDA13, MDA27, MDA30, PWM16, and PWM18).
Modulus load input signal status bit — This read-only status bit reflects the logic state of the
modulus load signal MMCnL (MDA12, MDA14, MDA28, MDA31, PWM17, and PWM19).
Freeze enable — This active high read/write control bit enables the MMCSM to recognize the
MIOB freeze signal.
Modulus load falling-edge sensitivity — This active high read/write control bit sets falling-edge
sensitivity for the MMCnL signal, such that a high-to-low transition causes a load of the
MMCSMCNT.
Modulus load rising-edge sensitivity
This active high read/write control bit sets rising-edge sensitivity for the MMCnL signal, such that
a low-to-high transition causes a load of the MMCSMCNT.
See
Clock select — These read/write control bits select the clock source for the modulus counter.
Either the rising edge or falling edge of the clock signal on the MMCnC signal may be selected,
as well as, the internal MMCSM prescaler output or disable mode (no clock source). See
Table 17-14
Reserved
Clock prescaler — This 8-bit data field is also accessible as an 8-bit data register. It stores the
two’s complement of the modulus value to be loaded into the built-in 8-bit clock prescaler. The
new value is loaded into the prescaler counter on the next counter overflow, or upon setting the
CLS1 — CLS0 bits for selecting the clock prescaler as the clock source.
Table 17-15
EDGP
Table 17-13
1
0
1
0
Table 17-12. MMCSMSCR Bit Descriptions
Table 17-13. MMCSMCNT Edge Sensitivity
for details about the clock selection.
gives the clock divide ratio according to the value of CP.
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 17-14. MMCSMCNT Clock Signal
MMCSMCNT load on rising and falling edges
MMCSMCNT load on falling edges
MMCSMCNT load on rising edges
None (disabled)
for details about edge sensitivity.
MMCSM clock prescaler
Clock signal falling-edge
Clock signal rising-edge
Clocking Selected
None (disable)
Description
Edge Sensitivity
Modular Input/Output Subsystem (MIOS14)
17-25