MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 415

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

In
Freescale Semiconductor
Figure
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Because ACS = 0, TRLX being set does not delay the assertion of the CS and WE strobes.
Because CSNT = 1, WE/BE is negated one clock cycle earlier than normal. (Refer to
CS is not negated one clock cycle earlier, since ACS = 00.
The total cycle length is three clock cycles, determined as follows:
— The basic memory cycle requires two clock cycles.
— One extra clock cycle is required due to the effect of TRLX on the negation of the WE/BE
Address
RD/WR
WE/BE
Figure 10-13. Relaxed Timing — Write Access (ACS = 11, SCY = 0, CSNT = 1, TRLX = 1)
Clock
10-14, notice the following:
Data
strobes.
OE
CS
TS
TA
MPC561/MPC563 Reference Manual, Rev. 1.2
ACS =11
ACS=00 & CSNT = 1
CSNT = 1
Memory Controller
Figure
10-8).
10-17