MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 822

MPC561MZP56

Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet

Specifications of MPC561MZP56

Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC561MZP56
Manufacturer:
FREESCALE
Quantity:
852
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC561MZP56
Manufacturer:
FREESCALE
Quantity:
852
Company:
Part Number:
MPC561MZP56
Quantity:
13
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Peripheral Pin Multiplexing (PPM) Module
TX_CONFIG_1 and TX_CONFIG_2 can only be written while PPM transmit mode is disabled
(PPMPCR[ENTX] = 0). While transmit is enabled these registers read as 0x00 and writing them will return
TEA (bus error access).
18.4.4
The two receive configuration registers control which internal modules will receive data from the PPM.
Each of the configuration registers contains eight separate 2-bit wide bit fields. Each of the 16 fields
controls a multiplexer that selects a 1-bit channel from the PPM data receive register to an internal module.
See
RX_CONFIG_1 and RX_CONFIG_2 can only be written while PPM receive mode is disabled
(PPMPCR[ENRX] = 0). While receive mode is enabled these registers read as 0x00 and writing them will
return TEA (bus error access).
18-16
SRESET
SRESET
SRESET
Table 18-6
Field
Field
Addr
Addr
Field
Addr
Receive Configuration Registers (RX_CONFIG_1 and
RX_CONFIG_2)
MSB
MSB
MSB
0
0
0
CH15
CH7
CH7
for more information on channel control and setting the channel values.
1
1
1
Figure 18-14. Transmit Configuration Register 1 (TX_CONFIG_1)
Figure 18-15. Transmit Configuration Register 2 (TX_CONFIG_2)
Figure 18-16. Receive Configuration Register 1 (RX_CONFIG_1)
2
2
2
CH14
CH6
CH6
3
3
3
MPC561/MPC563 Reference Manual, Rev. 1.2
4
4
4
CH13
CH5
CH5
5
5
5
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
6
6
6
CH12
CH4
CH4
0x30 5C06
0x30 5C08
0x30 5C0E
7
7
7
8
8
8
CH11
CH3
CH3
9
9
9
10
10
10
CH10
CH2
CH2
11
11
11
12
12
12
CH9
CH1
CH1
Freescale Semiconductor
13
13
13
14
14
14
CH0
CH8
CH0
LSB
LSB
LSB
15
15
15

Related parts for MPC561MZP56