MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 809

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

18.3
In order to reduce the number of signals on the devices, many signals have multiple functions and each
signal must be configured for access to any of these functions. The PPM module is designed to increase
the availability of MPC561/MPC563 signal multiplexed functions. It can do this is two ways:
18.3.1
The PPM communication sub-modules, PPM_MUX and PPM_SHIFTER, transfer data between the
MPC561/MPC563 and external devices. The PPM reduces the number of connections between devices by
allowing certain internal modules of the MCU to transmit and receive data serially, where without PPM
those internal modules would have to transmit and receive data in parallel. Data is routed through the PPM
using internal multiplexers. Communication between the internal modules and the PPM remains a parallel
connection, but the PPM connects to external devices by a serial link. The PPM can be configured for
different data transfer rates and data formats.
Freescale Semiconductor
1
2
3
•
•
Only accessible in Supervisor Mode.
This register is accessible in Test Mode only. Reads/Writes to this register when not in Test Mode will return TEA (bus
error access).
Accessible in Supervisor Mode and User Mode (when PPMMCR[SUPV]=0).
Access
S/U
S/U
S/U
S/U
S/U
S/U
S/U
By implementing a parallel-to-serial communication protocol,
By implementing internal signal shorting.
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Functional Description
3
3
3
3
3
3
3
PPM Parallel-to-Serial Communication Protocol
SCALE_TCLK_REG
SHORT_CH_REG
Register Name
RX_SHIFTER
SHORT_REG
Reserved
TX_DATA
Reserved
Reserved
GPDO
GPDI
Table 18-1. PPM Memory Map (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
0x30 5C2C –
0x30 5C1A
0x30 5C1C
0x30 5C1E
0x30 5C2A
0x30 5C20
0x30 5C22
0x30 5C24
0x30 5C26
0x30 5C28
0x30 5C7F
Address
Data is shifted in from signals PPM_RX[0:1]
Enables shorting of transmit data channels
Data to be transmitted on PPM_TX[0:1]
Enables shorting of internal signals
Establishes frequency of TCLK
General Purpose Data Out
General Purpose Data In
Peripheral Pin Multiplexing (PPM) Module
Usage
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18-3