MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 199

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

possible interrupt addresses to single-step such instructions. If this is unacceptable, other debug features
can be used. Refer to
Exception register settings.
Execution resumes at offset 0x0D00 from the base address indicated by MSR[IP].
3.15.4.12 Floating-Point Assist Exception (0x0E00)
A floating point assist exception occurs when the following conditions are true:
These conditions are summarized in the following equation:
Note that when ((MSR[FE0] | MSR[FE1]) AND FPSCR[FEX]) is set as a result of move to FPSCR, move
to MSR or rfi, a program exception is generated, rather than a floating-point assist exception.
A floating point assist exception also occurs when a tiny result is detected and the floating point underflow
exception is disabled (FPSCR[UE] = 0).
The register settings for floating-point assist exceptions are shown in
Freescale Semiconductor
1
•
•
•
Save/Restore Register 0 (SRR0)
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain a
compressed address.
Machine State Register (MSR)
A floating-point enabled exception condition is detected;
The corresponding floating-point enable bit in the FPSCR (floating point status and control
register) is set (exception enabled); and
MSR[FE0] | MSR[FE1] = 1
(MSR[FE0] | MSR[FE1]) AND FPSCR[FEX] = 1
Register Name
Register Name
Table 3-33. Register Settings following Floating-Point Assist Exceptions
Chapter 23, “Development
Table 3-32. Register Settings following a Trace Exception
1
1
MPC561/MPC563 Reference Manual, Rev. 1.2
DCMPEN
10:15
Other
Other
Bits
Bits
ME
1:4
LE
All
All
IP
Support,” for more information. See
Set to the effective address of the instruction following the
executed instruction
Cleared to 0
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI]
No change
Bit is copied from ILE
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Set to the effective address of the instruction that caused the
interrupt
Cleared to 0
Loaded from bits [16:31] of MSR. In the current
No change
Cleared to 0
Table
Description
Description
3-33.
Table 3-32
Central Processing Unit
for Trace
3-55