MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 162

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Central Processing Unit
3.7.5
The integer exception register (XER), SPR 1, is a user-level, 32-bit register.
The bit descriptions for XER, shown in
as a whole, not on intermediate results. For example, the result of the subtract from carrying (subfcx)
instruction is specified as the sum of three values. This instruction sets bits in the XER based on the entire
operation, not on an intermediate sum.
In most cases, reserved fields in registers are ignored when written to and return zero when read. However,
XER[16:23] are set to the value written to them and return that value when read.
3-18
1
CRn Bit
Here, the bit indicates the bit number in any one of the four-bit subfields, CR0–CR7
Reset
Bits
Field SO OV CA
Addr
0
1
0
1
2
3
1
MSB
Integer Exception Register (XER)
0
Less than, floating-point less than (LT, FL).
For integer compare instructions, (rA) < SIMM, UIMM, or (rB) (algebraic comparison) or (rA) SIMM, UIMM,
or (rB) (logical comparison). For floating-point compare instructions, (frA) < (frB).
Greater than, floating-point greater than (GT, FG).
For integer compare instructions, (rA) > SIMM, UIMM, or (rB) (algebraic comparison) or (rA) SIMM, UIMM,
or (rB) (logical comparison). For floating-point compare instructions, (frA) > (frB).
Equal, floating-point equal (EQ, FE).
For integer compare instructions, (rA) = SIMM, UIMM, or (rB).
For floating-point compare instructions, (frA) = (frB).
Summary overflow, floating-point unordered (SO, FU).
For integer compare instructions, this is a copy of the final state of XER[SO] at the completion of the
instruction. For floating-point compare instructions, one or both of (frA) and (frB) is not a number (NaN).
Name
SO
OV
Unchanged
1
2
Summary Overflow (SO). The summary overflow bit is set whenever an instruction sets the
overflow bit (OV) to indicate overflow and remains set until software clears it. It is not altered by
compare instructions or other instructions that cannot overflow.
Overflow (OV). The overflow bit is set to indicate that an overflow has occurred during execution
of an instruction. Integer and subtract instructions having OE=1 set OV if the carry out of bit 0 is
not equal to the carry out of bit 1, and clear it otherwise. The OV bit is not altered by compare
instructions or other instructions that cannot overflow.
Table 3-9. CRn Field Bit Settings for Compare Instructions
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Table 3-10. Integer Exception Register Bit Descriptions
Figure 3-8. Integer Exception Register (XER)
MPC561/MPC563 Reference Manual, Rev. 1.2
Table
00_0000_0000_0000_0000_0
3-10, are based on the operation of an instruction considered
—
Description
SPR 1
Description
Freescale Semiconductor
Unchanged
BYTES
LSB
31