MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 874

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

CDR3 Flash (UC3F) EEPROM
21-12
14:15
Bits
5:13
1
2
3
4
SBBLOCK Small block program and erase select. The SBBLOCK bits are write-protected by the SES bit.
PEGOOD Program/erase operation result. The PEGOOD bit is for status only. At the completion of a
Name
EPEE
B0EM
PEFI
—
program or erase operation using the embedded hardware algorithm, the hardware algorithm
will change the state of the PEGOOD bit to reflect whether or not the program or erase operation
was successful.
Note: PEGOOD will be set under the following conditions:
The PEGOOD bit is only valid after the hardware program/erase algorithm has cleared HVS.
PEGOOD is reset when either EHV is asserted or SES is cleared. See
diagram of when PEGOOD is valid.
0 program or erase operation failed
1 program or erase operation was successful
Program/erase fail indicator. The PEFI bit is a status qualifier for the PEGOOD bit and is valid
for the same times that PEGOOD is valid. In the event of an erase failure which returns
PEGOOD = 0, the PEFI bit provides diagnostic information for the cause of the erase failure.
If PEFI = 0, the erase failure occurred during the preprogramming step of the erase operation. If
PEFI = 1, the erase failure occurred during the actual erase or APDE steps of the erase
operation.
In the event of a program failure which returns PEGOOD = 0, the PEFI bit indicates a program
failure by reading as a 0. The PEFI bit should never return a 1 for a program failure.
NOTE: The PEFI bit is meaningful only while PEGOOD is valid and PEGOOD = 0. PEFI is valid
after HVS negates and prior to the assertion of EHV or negation of SES.
0 Program operation failed if PEGOOD = 0
1 Erase operation failed if PEGOOD = 0
EPEE pin status. The EPEE bit monitors the state of the external program/erase enable (EPEE)
input. The UC3F module samples the EPEE input when EHV is asserted and holds that sampled
state until EHV is negated.
0 high voltage operations are not possible
1 high voltage operations are possible
Block 0 EPEE pin status. The B0EM bit monitors the state of the Block 0 EPEE, B0EPEE, input.
The UC3F module samples the B0EPEE input when EHV is asserted and holds that sampled
value until EHV is negated.
If B0EM = 1 when EHV is asserted, high voltage operations such as program or erase are
enabled for either small block 0 or the lowest numbered block of the UC3F array regardless of
the state of EPEE.
If B0EM = 0 when EHV is asserted, high voltage operations are disabled for small block 0 or the
lowest numbered block of the UC3F array regardless of the state of EPEE.
0 High voltage operations are not possible for block 0 or lowest numbered block
1 High voltage operations are possible for block 0 or lowest numbered block.
Reserved
SBBLOCK selects the UC3F EEPROM small array blocks for program and erase operation.
When programming, only those blocks intended to be enabled for programming should have
their corresponding BLOCK[M] or SBBLOCK[M] bit set.
0 Small block M is not selected for program or erase
1 Small Block M is selected for program or erase
• No failure occurred
• No program or erase operation was requested (i.e., the Flash was protected)
Table 21-5. UC3FCTL Bit Descriptions (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
Description
Figure 21-5
Freescale Semiconductor
for a timing