MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 380

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

External Bus Interface
9.5.8.7
This signal is sent from the master to the slave to indicate that there is a data beat following the current
data beat. The master uses this signal to give the slave advance warning of the remaining data in the burst.
BDIP can also be used to terminate the burst cycle early. Refer to
Section 9.5.5, “Burst
Base Registers
9.5.9
The EBI uses three termination signals:
9.5.9.1
Transfer acknowledge (TA) indicates normal completion of the bus transfer. During a burst cycle, the slave
asserts this signal with every data beat returned or accepted.
9.5.9.2
A slave sends the BI signal to the master to indicate that the addressed device does not have burst
capability. If this signal is asserted, the master must transfer in multiple cycles and increment the address
for the slave to complete the burst transfer. For a system that does not use the burst mode at all, this signal
can be tied low permanently. Refer to
for BI options.
9.5.9.3
The TEA signal terminates a bus cycle under one or more bus error conditions. The current bus cycle must
be aborted. This signal overrides any other cycle termination signals, such as transfer acknowledge.
9.5.9.4
The transfer protocol was defined to avoid electrical contention on lines that can be driven by various
sources. To this end, a slave must not drive signals associated with the data transfer until the address phase
is completed and it recognizes the address as its own. The slave must disconnect from signals immediately
after it has acknowledged the cycle and no later than the termination of the next address phase cycle. This
means that the termination signals must be connected to power through a pull-up resistor to avoid the
situation in which a master samples an undefined value in any of these signals when no real slave is
addressed.
9-40
Refer to
1
•
•
•
Cases in which both TS and STS are asserted indicate normal cycles with the show cycle attribute.
Transfer acknowledge (TA)
Burst inhibit (BI)
Transfer error acknowledge (TEA)
Figure 9-28
Termination Signals
Burst Data in Progress
Transfer Acknowledge
Burst Inhibit
Transfer Error Acknowledge
Termination Signals Protocol
(BR0–BR3)” for memory controller BDIP options.
Mechanism” for more information. Refer to
and
Figure
MPC561/MPC563 Reference Manual, Rev. 1.2
9-29.
Section 10.9.3, “Memory Controller Base Registers
Section 9.5.4, “Burst
Section 10.9.3, “Memory Controller
Freescale Semiconductor
Transfer” and
(BR0–BR3)”