MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 217

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Base Address Register
Figure
Each table entry must contain a branch absolute (ba) instruction to the first instruction of an interrupt
service routine. Each table entry occupies two words (eight bytes) to support decompression on mode,
where a branch instruction can be more than 32 bits long.
The memory space allocated for the external interrupt relocation table is up to 2 Kbytes. If part of the
external interrupt relocation table entry is not used, it may be utilized for another purpose such as
instruction code space or data space.
In order to activate the external interrupt relocation feature, the following steps are required:
Freescale Semiconductor
1. Program the EIBADR register to the external interrupt branch table base address. See
2. Set the MSR[IP] bit.
3. Set the BBCMCR[EIR] bit. See
4-3.
Section 4.6.2.5, “External Interrupt Relocation Table Base Address Register
(BBCMCR),” for programming details.
If both the enhanced external interrupt relocation and exception table
relocation functions are activated simultaneously, the final external interrupt
vector is defined by EEIR mechanism.
When the EEIR function is activated, any branch instruction execution with
the 0xFFF0 0500 target address may cause unpredictable program
execution.
(EIBADR).” This is the base address of a branch table. See
MPC561/MPC563 Reference Manual, Rev. 1.2
Section 4.6.2.1, “BBC Module Configuration Register
NOTE
Burst Buffer Controller 2 Module
Table 6-4
(EIBADR).”
and
4-11