MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 842

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Time Processor Unit 3
19.4.2
This register is accessible only when the TPU is in test mode; see
Registers.”
19-12
1
SRESET
12:15
If all TPUs connected to a DPTRAM are stopped, the DPTRAM is accessible.
Bits
Bits
1:4
10
11
9
0
5
6
Field HOT4
Addr
Development Support Control Register (DSCR)
MSB
T2CSL
Name
PSCK
Name
TPU3
HOT4
CLKS
0
BLC
—
—
1
Standard prescaler clock. Note that this bit has no effect if the extended prescaler is selected
(EPSCKE = 1).
0 f
1 f
TPU3 enable. The TPU3 enable bit provides compatibility with the TPU. If running TPU code on
the TPU3, the microcode size should not be greater than 2 Kbytes and the TPU3 enable bit
should be cleared to zero. The TPU3 enable bit is write-once after reset. The reset value is one,
meaning that the TPU3 will operate in TPU3 mode.
0 TPU mode; zero is the TPU reset value
1 TPU3 mode; one is the TPU3 reset value
NOTE: The programmer should not change this value unless necessary when developing
custom TPU microcode.
TCR2 counter clock edge. This bit and the T2CG control bit determine the clock source for TCR2.
Refer to
Reserved. These bits are used for the IARB (interrupt arbitration ID) field in TPU3
implementations that use hardware interrupt arbitration.
Figure 19-6. DSCR — Development Support Control Register
Hang On T4
0 Exit wait on T4 state caused by assertion of HOT4
1 Enter wait on T4 state
Reserved
Branch Latch Control
0 Latch conditions into branch condition register before exiting halted state
1 Do not latch conditions into branch condition register before exiting the halted state or during
Stop clocks (to TCRs)
0 Do not stop TCRs
1 Stop TCRs during the halted state
the time-slot transition period
SYS
SYS
2
Table 19-7. TPUMCR Bit Description (continued)
÷ 32 is input to TCR1 prescaler, if standard prescaler is selected
÷ 4 is input to TCR1 prescaler, if standard prescaler is selected
Section 19.3.9, “Prescaler Control for
—
MPC561/MPC563 Reference Manual, Rev. 1.2
1
3
Table 19-8. DSCR Bit Descriptions
0x30 4004 (TPU_A), 0x30_4404 (TPU_B)
4
BLC CLKS
5
0000_0000_0000_0000
6
Description
Description
7
FRZ
TCR2” for details.
8
CCL
Section 19.4.14, “Factory Test
9
BP
10
BC
11
BH
12
Freescale Semiconductor
BL
13
BM
14
LSB
BT
15