MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 447

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

11.7.5
The L2U performs the following sequence of actions for an L-bus read show cycle.
11.7.6
The following are the guidelines for L2U show cycle support:
Freescale Semiconductor
2. Latches the address and the data of the L-bus access, along with all address attributes
3. Waits for the termination of the L-bus access and latches the termination status (data error)
4. Arbitrate for the U-bus, and when granted, starts the U-bus access, asserting show cycle request on
5. When the L2U module has U-bus data bus grant, it drives the data phase termination handshakes
6. Releases the L-bus
1. Arbitrates for the L-bus to prevent any other L-bus cycle from starting
2. Latches the address of the L-bus access, along with all address attributes
3. Waits for the data phase termination on the L-bus and latches the read data, and the termination
4. Arbitrates for the U-bus, and when granted, starts the U-bus access, asserting the show cycle
5. When the L2U module has U-bus data bus grant, it drives the read data and the data phase
6. Release the L-bus.
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the U-bus, along with address, attributes and the write data. The L2U module provides address
recognition and acknowledgment for the address phase. If the no-show cycle indicator from the
U-bus is asserted, the L2U does not start the show cycle. The L2U module releases the U-bus until
the no-show cycle indicator is negated and then arbitrates for the U-bus again.
on the U-bus.
status from the L-bus
request on the U-bus, along with address attributes. The L2U module provides address
recognition/acknowledgment for the address phase. If the no-show cycle indicator from the U-bus
is asserted, the L2U does not start the show cycle. The L2U module releases the U-bus until the
no-show cycle indicator is negated and then arbitrates for the U-bus again.
termination handshakes on the U-bus
The L2U module provides address and data for all qualifying L-bus cycles when the appropriate
mode bits are set in the L2U_MCR.
The L2U-module-only provides show cycles L-bus activity that is not targeted for the U-bus or the
L2U module internal registers, regardless of the termination status of such activity.
The L2U module does not provide show cycle access to any MPC500 special purpose register.
The L2U does not start a show cycle for an L-bus access that is retried. This decision to not start
the show cycle causes a clock delay before the cycle can be retried, since the L2U module will have
arbitrated away the L-bus immediately on detecting the show cycle, before the retry information is
available.
The L2U module does not show cycle any L-bus activity that is aborted.
The L2U module does not access the U-bus if the USIU inhibits show cycle activity on the U-bus.
L-Bus Read Show Cycle Flow
Show Cycle Support Guidelines
MPC561/MPC563 Reference Manual, Rev. 1.2
L-Bus to U-Bus Interface (L2U)
11-11