MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1316

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

66-MHz Electrical Characteristics
G.7
Note: (V
G-10
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
This characteristic is for 5-V output and 5-V input pins.
0.3V > V
Within this range, no significant injection will be seen. See QADC64 Disruptive Input Current (I
During reset all 2.6V and 2.6V/5V pads will leak up to 10µA to QVDDL if the pad has a voltage > QVDDL.
Maximum leakage occurs at maximum operating temperature. Current decreases by approximately one-half for each
8 to 12 °C, in the ambient temperature range of 50 to 125 °C.
All bus pins support two drive strengths capabilities, 25 pF and 50 pF. Current drive is less at the 25-pF
capacitive load. Both modes achieve 66-MHz timing.
Only IRQ, TPU, MIOS, GPIO, QADC (when digital inputs) and RESET pins have hysteresis, thus there is no hysteresis
specification on all other pins
Transient currents can reach 50mA.
KAPWR and IRAMSTBY can be powered-up prior to any other supply or at the same time as the other 2.6 V supplies.
IRAMSTBY must lead or coincide with VDD; however it can lag KAPWR.
This parameter is periodically sampled rather than 100% tested
Up to 0.5 V during power up/down.
To obtain full-range results, V
When using the QADC in legacy mode it is recommended to connect this pin to 2.6V or 3.3V, however it can be
connected to 0V or 5V without damage to the device.
A resistor must be placed in series with the IRAMSTBY power supply. Refer to
Guidelines.”
All injection current is transferred to the V
power supply within the specified voltage range.
Absolute maximum voltage ratings for each pin (see
Total injection current for all I/O pins on the chip must not exceed 20 mA (sustained current). Exceeding this limit can
cause disruption of normal operation.
Current refers to two QADC64 modules operating simultaneously.
Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs
greater than V
presence of the sample amplifier. Other channels are not affected by non-disruptive conditions.
DD
Oscillator Startup time (for typical crystal capacitive load)
4-MHz crystal
20-MHz crystal
PLL Lock Time
PLL Operating Range
Crystal Operating Range, MODCK=0b010,0b110
MODCK[1:3] = 0b001, 0b011, 0b100, 0b101, 0b111
PLL Jitter
PLL Jitter (averaged over 10 µs)
Limp Mode Clock Out Frequency
Oscillator Bias Current (XTAL)
4 MHz
20 MHz
Oscillator and PLL Electrical Characteristics
= 2.6 V ± 0.1 V, V
DDA
or V
RH
DDH
and 0x000 for values less than V
, whichever is greater.
DDH
Characteristic
2
= 5.0 V ± 0.25 V, T
SSA
MPC561/MPC563 Reference Manual, Rev. 1.2
≤ V
RL
Table G-5. Oscillator and PLL
≤ V
DDH
INDC
. An external load is required to dissipate this current to maintain the
A
= T
≤ V
RL
L
RH
Table
. This assumes that V
to T
≤ V
H
)
DDA
G-1) must also be met during this condition.
OSCstart20
OSCstart4
F
F
Symbol
CRYSTAL
T
VCOOUT
F
I
F
LOCK
BIAS
JIT10
—
JIT
RH
≤ V
-0.3%
| 1.5 |
Appendix C, “Clock and Board
Min
-1%
30
15
3
—
3
DDA
3
and V
Typica
11
l
RL
≥ V
NA
Freescale Semiconductor
).
SSA
+0.3%
1000
| 0.8 |
| 4.0 |
+1%
Max
132
17
10
10
25
5
due to the
3
1
Clocks
Input
MHz
MHz
MHz
MHz
Unit
mA
mA
ms
ms
—