MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 233

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Chapter 5
Unified System Interface Unit (USIU) Overview
The unified system interface unit (USIU) of the MPC561/MPC563 consists of several functional modules
that control system start-up, system initialization and operation, system protection, and the external system
bus. The MPC561/MPC563 USIU functions include the following and are discussed in the designated
chapters:
The USIU provides system configuration and protection features that control the overall system
configuration and supply various monitors and timers including the bus monitor, software watchdog timer,
periodic interrupt timer, decrementer, time base, and real-time clock. Freeze support and low power stop
is provided. The interrupt controller supports up to eight external interrupts, eight levels for all internal
USIU interrupt sources and 32 levels for internal peripheral modules on the IMB bus. It has an enhanced
mode of operation, which simplifies the MPC561/MPC563 interrupt structure and speeds up interrupt
processing.
Additionally, the USIU provides several pinout configurations that allow up to 64 general-purpose I/O,
external 32-bit port that supports internal and external masters, and various debug functions.
Reset logic for the MPC561/MPC563 provides soft and hard resets, checkstop and watchdog resets, and
other types of reset. The reset status register (RSR) reflects the most recent source to cause a reset.
The clock synthesizer generates the clock signals used by the USIU as well as the other modules and
external devices. This circuitry can generate a system clock from a range of crystals, typically in the 4 MHz
or 20 MHz range.
The USIU supports various low-power modes. Each one supplies a different range of power consumption,
functionality and wake-up time. Refer to
The EBI handles the transfer of information between the internal busses and the memory or peripherals in
the external address space. The MPC561/MPC563 is designed to allow external bus masters to request and
obtain mastership of the system bus, and if required access the on-chip memory and registers. Refer to
Chapter 9, “External Bus
The memory controller module provides glueless interface to many types of memory devices and
peripherals. It supports up to four memory banks. Refer to
Freescale Semiconductor
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•
•
•
•
System configuration and protection with GPIO capability and an enhanced interrupt controller.
Refer to
System reset monitoring and generation, refer to
Clock synthesis, power management, and debug support. Refer to
Control.”
External bus interface (EBI), refer to
Memory controller that supports four memory banks. Refer to
Chapter 6, “System Configuration and
Interface,” for details.
MPC561/MPC563 Reference Manual, Rev. 1.2
Chapter 8, “Clocks and Power
Chapter 9, “External Bus
Protection.”
Chapter 7,
Chapter 10, “Memory
“Reset.”
Chapter 10, “Memory
Interface.”
Control,” for details.
Chapter 8, “Clocks and Power
Controller,” for details.
Controller.”
5-1