MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1116

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Internal Memory Map
B-6
0x2F C010
0x2F C014
0x2F C018
0x2F C01C
0x2F C020
0x2F C024
0x2F C028
0x2F C02C
0x2F C030
0x2F C038
0x2F C03C
0x2F C040 —
0x2F C044
0x2F C048 —
0x2F C04C
0x2F C050 —
0x2F C054
0x2F C0FC —
0x2F C0FF
0x2F C100
0x2F C104
0x2F C108
Address
read only
Access
—
U,
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
Table B-5. USIU (Unified System Interface Unit) (continued)
SISR2 — SISR3 SISR2 and SISR3 Registers
SIPEND2 —
SIMASK2 —
SGPIODT1
SGPIODT2
SGPIOCR
SIPEND3
SIMASK3
PDMCR2
SIPEND
SIMASK
Symbol
PDMCR
SIVEC
EMCR
TESR
SIEL
OR0
BR0
BR1
MPC561/MPC563 Reference Manual, Rev. 1.2
—
Memory Controller Registers
Interrupt Pending Register
See
Interrupt Mask Register
SIMASK is a 32-bit read/write register. Each bit
in the register corresponds to an interrupt
request bit in the SIPEND register.
Interrupt Edge Level Mask.
See
Interrupt Vector.
See
Transfer Error Status Register
See
USIU General-Purpose I/O Data Register 1
See
USIU General-Purpose I/O Data Register 2
See
USIU General-Purpose I/O Control Register
See
External Master Mode Control Register
See
Pads Module Configuration Register 2
See
Pads Module Configuration Register
See
Interrupt Pending Registers 2 and 3
See
Interrupt Mask Register and Interrupt Mask
Registers 2 and 3
See
See
Reserved
Base Register 0.
See
Option Register 0.
See
Base Register 1.
See
Section 6.2.2.2.1
Section 6.2.2.2.7
Section 6.2.2.2.8
Table 6-17
Table 6-23
Table 6-24
Table 6-25
Table 6-13
Table 2-6
Table 2-5
Section 6.2.2.2.1
Section 6.2.2.2.9
Section 6.2.2.2.9
Table 10-8
Table 10-10
Table 10-8
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
Register
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
Freescale Semiconductor
Size
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
—
Reset
—
—
H
H
H
H
H
H
H
H
H
H
S
S
S
S
S
S