MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 680

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Queued Serial Multi-Channel Module
15.8.3
The block diagram of the enhancements to the SCI transmitter is shown in
15-62
12:15
Bits
8:11
5
6
7
QSCI1 Transmitter Block Diagram
QRPNT
QPEND
QBHE
Name
QBHF
QTHE
Receiver queue bottom-half full. QBHF is set when the receive queue locations SCRQ[8:15] are
completely filled with new data received via the serial shifter. QBHF is cleared when register
QSCI1SR is read with QBHF set, followed by a write of QBHF to zero.
0 The queue locations SCRQ[8:15] are partially filled with newly received data or is empty
1 The queue locations SCRQ[8:15] are completely full of newly received data
Transmitter queue top-half empty. QTHE is set when all the data frames in the transmit queue
locations SCTQ[0:7] have been transferred to the transmit serial shifter. QTHE is cleared when
register QSCI1SR is read with QTHE set, followed by a write of QTHE to zero.
0 The queue locations SCTQ[0:7] still contain data to be sent to the transmit serial shifter
1 New data may now be written to the queue locations SCTQ[0:7]
Transmitter queue bottom-half empty. QBHE is set when all the data frames in the transmit queue
locations SCTQ[8:15] has been transferred to the transmit serial shifter. QBHE is cleared when
register QSCI1SR is read with QBHE set, followed by a write of QBHE to zero.
0 The queue locations SCTQ[8:15] still contain data to be sent to the transmit serial shifter
1 New data may now be written to the queue locations SCTQ[8:15]
Queue receive pointer. QRPNT is a 4-bit counter used to indicate the position where the next
valid data frame will be stored within the receive queue. This field is writable in test mode only;
otherwise it is read-only.
Queue pending. QPEND is a 4-bit decrementer used to indicate the number of data frames in the
queue that are awaiting transfer to the SC1DR. This field is writable in test mode only; otherwise
it is read-only. From 1 (QPEND = 0b0000) to 16 (or done, QPEND = 1111) data frames can be
specified.
Table 15-33. QSCI1SR Bit Descriptions (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
Description
Figure
15-33.
Freescale Semiconductor