MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 315
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MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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The clocks GCLK1_50 and GCLK2_50 frequency is:
Figure 8-7
8.5.2
CLKOUT has the same frequency as the general system clock (GCLK2_50). Unlike the main system clock
GCLK1/GCLK2 however, CLKOUT (and GCLK2_50) represents the external bus clock, and thus will be
one-half of the main system clock if the external bus is running at half speed (EBDF = 0b01). The
CLKOUT frequency (system frequency) defaults to VCO/2. CLKOUT can drive full, half, or quarter
strength; it can also be disabled. The drive strength is controlled in the system clock and reset-control
register (SCCR) by the COM[0:1] and CQDS bits. (See
(SCCR)”). Disabling or decreasing the strength of CLKOUT can reduce power consumption, noise, and
electromagnetic interference on the printed circuit board.
When the PLL is acquiring lock, the CLKOUT signal is disabled and remains in the low state (provided
that BUCS = 0).
Freescale Semiconductor
GCLK1
GCLK2
GCLK1_50
(EBDF = 00)
GCLK2_50
(EBDF = 00)
CLKOUT
(EBDF = 00)
GCLK1_50
(EBDF = 01)
GCLK2_50
(EBDF = 01)
CLKOUT
(EBDF = 01)
shows the timing of USIU clocks when DFNH = 1 or DFNL = 0.
Clock Out (CLKOUT)
Figure 8-7. Clocks Timing For DFNH = 1 (or DFNL = 0)
FREQ 50
MPC561/MPC563 Reference Manual, Rev. 1.2
=
------------------------------------------------------------------ -
(
2
DFNH
FREQsysmax
)or 2
(
DFNL
Section 8.11.1, “System Clock Control Register
+
1
)
x
--------------------------
EBDF
1
+
1
Clocks and Power Control
8-13
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