MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 401

MPC561MZP56

Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet

Specifications of MPC561MZP56

Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant

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a 16-bit boot EPROM and CS1 is used for a 32-bit SRAM. The WE/BE[0:3] signals are used both to
program the EPROM and to enable write access to various bytes in the RAM.
10.2
The memory controller consists of a basic machine that handles the memory access cycle: the
general-purpose chip-select machine (GPCM).
When any of the internal masters request a new access to external memory, the address of the transfer (with
17 bits having a mask) and the address type (with three bits having a mask) are compared to each one of
the valid banks defined in the memory controller. Refer to
Freescale Semiconductor
Memory Controller Architecture
MPC500
WE/BE[0:3]
Figure 10-3. MPC561/MPC563 Simple System Configuration
Address
Data
CS0
CS1
OE
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure
[0:31]
[0:15]
10-4.
Address
WE/BE[0:1]
DATA[0:15]
Address
CE
WE/BE[0:3]
Data
OE
CE
OE
EPROM
SRAM
Memory Controller
10-3

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