MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 654

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Queued Serial Multi-Channel Module
15.6.5.3
The DSCK bit in each command RAM byte inserts either a standard (DSCK = 0) or user-specified (DSCK
= 1) delay from chip-select assertion until the leading edge of the serial clock. The DSCKL field in SPCR1
determines the length of the user-defined delay before the assertion of SCK. The following expression
determines the actual delay before SCK when DSCKL is in the range of 1–127:
When DSCK equals zero, DSCKL is not used. Instead, the PCS valid-to-SCK transition is one-half the
SCK period.
15.6.5.4
Delay after transfer can be used to provide a peripheral deselect interval. A delay can also be inserted
between consecutive transfers to allow serial A/D converters to complete conversion. Writing a value to
the DTL field in SPCR1 specifies a delay period. The DT bit in each command RAM byte determines
whether the standard delay period (DT = 0) or the specified delay period (DT = 1) is used. The following
expression is used to calculate the delay:
A zero value for DTL causes a delay-after-transfer value of 8192 ÷ IMB3 clock frequency (204.8 µs with
a 40-MHz IMB3 clock).
If DT is zero in a command RAM byte, a standard delay is inserted.
15-36
Delay Before Transfer
Delay After Transfer
Table 15-21. Example SCK Frequencies with a 40-MHz IMB3 Clock (continued)
where DTL is in the range from one to 255.
A zero value for DSCKL causes a delay of 128 IMB3 clocks, which equals
3.2 µs for a 40-MHz IMB3 clock. Because of design limits, a DSCKL value
of one defaults to the same timing as a value of two.
Division Ratio
MPC561/MPC563 Reference Manual, Rev. 1.2
PCS to SCK Delay
280
510
14
28
58
Standard Delay after Transfer
Delay after Transfer
SPBR Value
NOTE
140
255
14
29
=
7
DSCKL
------------------- -
f SYS
=
32xDTL
-------------------- -
f SYS
Frequency
78.43 kHz
2.86 MHz
1.43 MHz
689 kHz
143 kHz
=
SCK
-------------
f SYS
17
Freescale Semiconductor
Eqn. 15-3