MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 156

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Central Processing Unit
Unless otherwise noted, reserved fields should be written with a zero when written and return zero when
read. An exception to this rule is XER[16:23]; see
These bits are set to the value written to them and return that value when read.
3.7
The UISA registers can be accessed by either user- or supervisor-level instructions. The general-purpose
registers are accessed through instruction operands.
3.7.1
Integer data is manipulated in the integer unit’s thirty-two 32-bit GPRs, shown below. These registers are
accessed as source and destination registers through operands in the instruction syntax.
3.7.2
The PowerPC ISA architecture provides 32 64-bit FPRs. These registers are accessed as source and
destination registers through operands in floating-point instructions. Each FPR supports the
double-precision, floating-point format. Every instruction that interprets the contents of an FPR as a
3-12
Reset
User Instruction Set Architecture (UISA)
Register Set
General-Purpose Registers (GPRs)
Floating-Point Registers (FPRs)
MSB
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
1
SPR Number
All development-support SPRs are implementation-specific.
(Decimal)
158
159
630
Table 3-3. Development Support SPRs
Figure 3-4. General-Purpose Registers (GPRs)
MPC561/MPC563 Reference Manual, Rev. 1.2
I-bus Support Control Register (ICTRL)
See
Breakpoint Address Register (BAR)
See
Development Port Data Register (DPDR)
See
(DPDR),” for bit descriptions.
Table 23-26
Table 23-28
Section 23.6.13, “Development Port Data Register
Special-Purpose Register
for bit descriptions.
for bit descriptions.
Section 3.7.5, “Integer Exception Register
Unchanged
GPR31
GPR0
GPR1
. . .
. . .
1
(continued)
Freescale Semiconductor
(XER).”
LSB
31