MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 573

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Freescale Semiconductor
Reset
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•
•
•
Field
Addr
Bits
conversions restart with the first CCW entry in queue 2 or the first CCW of the queue 2 sub-queue
being executed when queue 2 was suspended. Alternately, conversions can restart with the aborted
queue 2 CCW entry. The RESUME bit in QACR2 allows the software to select where queue 2
begins after suspension. By choosing to re-execute all of the suspended queue 2 queue and
sub-queue CCWs, all of the samples are guaranteed to have been taken during the same scan pass.
However, a high trigger event rate for queue 1 can prohibit the completion of queue 2. If this
occurs, the software may choose to begin execution of queue 2 with the aborted CCW entry.
Software can change the queue operating mode to disabled mode. Any conversion in progress for
that queue is aborted. Putting a queue into the disabled mode does not power down the converter.
Software can change the queue operating mode to another valid mode. Any conversion in progress
for that queue is aborted. The queue restarts at the beginning of the queue, once an appropriate
trigger event occurs.
For low power operation, software can set the stop mode bit to prepare the module for a loss of
clocks. The QADC64E aborts any conversion in progress when the stop mode is entered.
When the freeze enable bit is set by software and the IMB3 internal FREEZE line is asserted, the
QADC64E freezes at the end of the conversion in progress. When internal FREEZE is negated, the
QADC64E resumes queue execution beginning with the next CCW entry. Refer to
“Configuration and Control Using the IMB3
0:5
6
7
MSB
0
Name
REF
—
P
1
2
Figure 14-16. Conversion Command Word Table (CCW)
Reserved
Pause. The pause bit allows software to create sub-queues within queue 1 and queue 2.
The QADC64E performs the conversion specified by the CCW with the pause bit set, and
then the queue enters the pause state. Another trigger event causes execution to continue
from the pause to the next CCW.
0 Do not enter the pause state after execution of the current CCW
1 Enter the pause state after execution of the current CCW
NOTE: The pause bit will not cause the queue to pause in the software controlled modes
or external gated modes.
Alternate Reference Enabled. Setting REF high in the CCW enables the use of an alternate
reference.
0 VRH is used as high reference
1 AltRef signal is used as the high reference
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3
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 14-19. CCW Bit Descriptions
0x30 4A00 – 0x30 4A7F, 0x30 4E00 – 0x30 4E7F
4
5
P
6
REF
Unaffected
Interface” for more information.
7
Description
IST
8
9
10
QADC64E Enhanced Mode Operation
11
CHAN[6:0]
12
13
Section 14.4.7,
14
LSB
15
14-31