MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 120

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Signal Descriptions
2.3
Bits in the PDMCR (which resides in the SIU memory map) control the slew rate and weak
pull-up/pull-down characteristics of some signals; refer to
PORESET/TRST signal resets all the PDMCR bits asynchronously.
Table 2-5
2-22
HRESET
HRESET
Bits
0:5
Field
Field
Addr
Pad Module Configuration Register (PDMCR)
contains bit descriptions for the PDMCR.
SLRC[0:5]
MSB
Name
16
0
17
1
SLRC0 controls the slew rate of signals on the following modules: TPU3, QADC64E, SGPIOA,
SGPIOD, SGPIOC. For the slew rate refer to
0 Slew rate controlled
1 Not slew rate controlled
SLRC1 controls the slew rate of signals on the following modules: QSPI, TouCAN_A, TouCAN_B.
For the slew rate refer to
0 Slew rate controlled
1 Not slew rate controlled
SLRC2 controls the slew rate of signals on the QSCI in QSMCM . For the slew rate refer to
Appendix F, “Electrical
0 Slew rate controlled
1 Not slew rate controlled
SLRC3 controls the slew rate of signals on the following modules: MIOS14 except
MPWM2/PPM_TX1 and MPWM3 signal. For the slew rate refer to
Characteristics.”
0 Slew rate controlled
1 Not slew rate controlled
SLRC4 controls the slew rate of the MIOS14 MPWM2 signal. For the slew rate refer to
“Electrical
0 Slew rate controlled
1 Not slew rate controlled
SLRC5 controls the slew rate of the MIOS14 MPWM3 signal. For the slew rate refer to
“Electrical
0 Slew rate controlled
1 Not slew rate controlled
18
Figure 2-2. Pads Module Configuration Register (PDMCR)
SLRC
2
19
3
Characteristics.”
Characteristics.”
MPC561/MPC563 Reference Manual, Rev. 1.2
20
4
Table 2-5. PDMCR Field Descriptions
21
5
Characteristics.”
Appendix F, “Electrical
PRDS SPRDS T2CLK_PU
22
6
0000_0000_0000_0000
0000_0000_0000_0000
0x2F C03C
23
7
—
Description
Appendix F, “Electrical
Appendix F, “Electrical
Characteristics.”
24
8
25
9
10
26
Appendix F, “Electrical
Characteristics.”
PULL_DIS
11
27
Characteristics.” The
12
28
Freescale Semiconductor
13
29
Appendix F,
Appendix F,
14
30
LSB
—
15
31