MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 105

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Freescale Semiconductor
PORESET / TRST
HRESET
SRESET
SGPIOC6 / FRZ / PTR
SGPIOC7 / IRQOUT/ LWP0
Signal Name
Table 2-1. MPC561/MPC563 Signal Descriptions (continued)
Signals
No. of
1
1
1
1
1
MPC561/MPC563 Reference Manual, Rev. 1.2
Type
I/O
I/O
I/O
I/O
O
O
O
O
I
I
PORESET /
TRST
HRESET
SRESET
PTR
LWP0
Function after
Development and Debug
Reset
System Control
1
Power-On Reset. This signal should be activated as a result
of a voltage failure on the keep-alive power supply. The
signal has a glitch detector to ensure that low spikes of less
than 20 ns are rejected. The internal PORESET / TRST
signal is asserted only if PORESET / TRST is asserted for
more than 100 ns. See
on timing.
Test Reset. This input provides asynchronous reset to the
test logic (JTAG).
Hard Reset. The reset controller can detect an external
assertion of HRESET only if it occurs while the
MPC561/MPC563 is not asserting reset. After negation of
HRESET or SRESET is detected, a 16-cycle period is taken
before testing the presence of an external reset.
The internal HRESET signal is considered asserted only
when assertion lasts for more than 100 ns. To meet external
timing requirements, an external pull-up device is required
to negate HRESET. See
on timing.
Soft Reset. The reset controller can detect an external
assertion of SRESET only if it occurs while the
MPC561/MPC563 is not asserting reset. After negation of
HRESET or SRESET is detected, a 16-cycle period is taken
before testing the presence of an external soft reset. To
meet external timing requirements, an external pull-up
device is required to negate SRESET. See
“Reset,” for more details on timing.
Port SGPIOC6. Allows the signals to be used as
general-purpose inputs/outputs.
Freeze. Indicates that the RCPU is in debug stopped mode.
Program Trace. Indicates an instruction fetch is taking place
(for program flow tracking).
Port SGPIOC7. Allows the signal to be used as
general-purpose inputs/outputs.
Interrupt Out. Indicates that an interrupt has been requested
to all external devices.
Load/Store Watchpoint 0. This output signal reports the
detection of a data watchpoint in the program flow executed
by the RCPU. See
more details.
Chapter 23, “Development
Description
Chapter 7,
Chapter 7,
“Reset,” for more details
“Reset,” for more details
Signal Descriptions
Chapter 7,
Support,” for
2-7