MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 280

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

System Configuration and Protection
6.2.2.4
The following sections describe registers associated with the system timers. These facilities are powered
by the KAPWR and can preserve their value when the main power supply is off. Refer to
“Pre-Divider,” for details on the required actions needed in order to guarantee this data retention.
A list of KAPWR registers affected by the key/lock mechanism is found in
6.2.2.4.1
The 32-bit decrementer register is defined by the PowerPC architecture. The values stored in this register
are used by a down counter to cause decrementer exceptions. The decrementer causes an exception
whenever bit zero changes from a logic zero to a logic one. A read of this register always returns the current
count value from the down counter.
Contents of this register can be read or written to by the mfspr or the mtspr instruction. The decrementer
register is reset by PORESET. HRESET and SRESET do not affect this register. The decrementer is
powered by standby power and can continue to count when standby power is applied.
Decrementer counts down the time base clock and the counting is enabled by TBE bit in TBCSR register
Section 6.2.2.4.4, “Time Base Control and Status Register
Refer to
6.2.2.4.2
The TB is a 64-bit register containing a 64-bit integer that is incremented periodically. There is no
automatic initialization of the TB; the system software must perform this initialization. The contents of the
6-40
PORESET
20:25
28:31
HRESET
SRESET
Bits
26
27
Field
Addr
Section 3.9.5, “Decrementer Register
System Timer Registers
Name
DEXT
MSB
DBM
Decrementer Register (DEC)
Time Base SPRs (TB)
0
—
—
Reserved
Data external transfer error acknowledge. This bit is set if the cycle was terminated by an
externally generated TEA signal when a data load or store is requested by an internal master.
Data transfer monitor time out. This bit is set if the cycle was terminated by a bus monitor time-out
when a data load or store is requested by an internal master.
Reserved
Table 6-17. TESR Bit Descriptions (continued)
Figure 6-29. Decrementer Register (DEC)
MPC561/MPC563 Reference Manual, Rev. 1.2
0000_0000_0000_0000_0000_0000_0000_0000
DECREMENTING COUNTER
(DEC)” for more information on this register.
Unaffected
SPR 22
Description
(TBSCR).”
Table
8-8.
Freescale Semiconductor
Section 8.2.3,
LSB
31