MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1033

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

24.10.4.2 Read Operation
For a read access to internal READI registers, the following sequence of operations need to be performed
via the auxiliary port:
24.10.5 Error Handling
The READI module handles the various error conditions in the manner shown in the following sections.
24.10.5.1 Access Alignment
The READI module will force address alignment based on the word size field (SZ) value. If the SZ field
indicates word (32-bit) access, the least significant two bits of the read/write address field (RWAD) are
ignored. If the SZ field indicates half-word (16-bit) access, the least significant bit of the read/write address
field (RWAD) is ignored.
24.10.5.2 L-Bus Address Error
An address error occurs on the L-bus when the address phase of a cycle is not completed normally. This
could occur because of address not being valid or the address map not being valid. In such cases:
24.10.5.3 L-Bus Data Error
L-bus data error is signalled due to:
Freescale Semiconductor
2. The download request public message contains:
3. After the data has been written to the targeted register, the device ready for upload/download public
1. The tool confirms that the device is ready before transmitting upload request public message
2. The upload request public message contains:
3. The upload/download information public message (TCODE=19) is transmitted to the tool along
1. The access is terminated without retrying.
2. The SC bit of the RWA is reset. Block accesses do not continue.
3. The error message (TCODE = 8) is transmitted (error code 0b00011). Refer to
a) TCODE(18)
b) Access opcode, which specifies the register where data needs to be written, (e.g., access opcode
c) Data to be written to the register.
message (TCODE = 16) is transmitted to the tool indicating that the device is ready for next access.
(TCODE = 17).
a) TCODE(17)
b) Access opcode, which specifies the register where data needs to be read from, (for example,
with the data read from the targeted register indicating that the device is ready for next access.
0x14 indicates that DTA1 register is the target register).
access opcode 0x14 indicates that DTA1 register is the target register).
MPC561/MPC563 Reference Manual, Rev. 1.2
Table
24-20.
READI Module
24-65