MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 311

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

the input source to the SPLL (main system oscillator or EXTCLK). MODCK1, MODCK2, and MODCK3
together determine the multiplication factor at reset and the functionality of limp mode.
If the configuration of PITRTCLK and TMBCLK and the SPLL multiplication factor is to remain
unchanged in power-down low-power mode, the MODCK signals should not be sampled at wake-up from
this mode. In this case the PORESET pin should remain negated and HRESET should be asserted during
the power supply wake-up stage.
When MODCK1 is cleared, the output of the main oscillator is selected as the input to the SPLL. When
MODCK1 is asserted, the external clock input (EXTCLK pin) is selected as the input to the SPLL. In all
cases, the system clock frequency (freq
that freq
The TBS bit in the SCCR selects the time base clock to be either the SPLL input clock or GCLK2. When
the backup clock is functioning as the system clock, the backup clock is automatically selected as the time
base clock source.
The PITRTCLK frequency and source are specified by the RTDIV and RTSEL bits in the SCCR. When
the backup clock is functioning as the system clock, the backup clock is automatically selected as the time
base clock source.
When the PORESET pin is negated (driven to a high value), the MODCK1, MODCK2, and MODCK3
values are not affected. They remain the same as they were defined during the most recent power-on reset.
Table 8-1
Freescale Semiconductor
MODCK[1:3]
gclk2(max)
000
001
010
011
shows the clock configuration modes during power-on reset (PORESET asserted).
The MODCK[1:3] are shared functions with IRQ[5:7]. If IRQ[5:7] are used
as interrupts, the interrupt source should be removed during PORESET to
insure the MODCK pins are in the correct state on the rising edge of
PORESET.
1
occurs when the DFNH bits are cleared.
LME
0
0
1
1
RTSEL
0
0
0
0
Table 8-1. Reset Clocks Source Configuration
Default Values after PORESET
MPC561/MPC563 Reference Manual, Rev. 1.2
RTDIV
0
1
1
1
gclk2
) can be reduced by the DFNH[0:2] bits in the SCCR. Note
MF + 1
1
1
5
1
NOTE
Division
PITCLK
256
256
256
4
TMBCLK
Division
16
16
4
4
Used for testing purposes.
Normal operation, PLL enabled.
Main timing reference is crystal
osc (20 MHz).
Limp mode disabled.
Normal operation, PLL enabled.
Main timing reference is crystal
osc (4 MHz).
Limp mode enabled.
Normal operation, PLL enabled.
Main timing reference is crystal
osc (20 MHz).
Limp mode enabled.
SPLL Options
Clocks and Power Control
8-9