MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1106

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

MPC562/MPC564 Compression Features
A.4
The DCCR fields are programmed to achieve maximum flexibility in the vocabulary tables placement into
the two DECRAM banks under constraints, implied by hardware, which are:
A-18
1
•
Serialize
Control
MPC562/MPC564 only.
29:31
Bits
(SER)
28
A bypass field must always be in the second field of the compressed instruction
0
0
0
0
1
1
1
1
Decompressor Class Configuration Registers (DCCR0-15)
Mnemonic
ISCT_SER
Instruction
(ISCTL)
IFM
Fetch
00
01
10
11
00
01
10
11
Ignore first match, only for I-bus
breakpoints
RCPU serialize control and
Instruction fetch show cycle
RCPU is fully serialized and show cycles will be performed for all fetched instructions (reset
value)
RCPU is fully serialized and show cycles will be performed for all changes in the program flow
RCPU is fully serialized and show cycles will be performed for all indirect changes in the
program flow
RCPU is fully serialized and no show cycles will be performed for fetched instructions
Illegal. This mode should not be selected.
RCPU is not serialized (normal mode) and show cycles will be performed for all changes in
the program flow
RCPU is not serialized (normal mode) and show cycles will be performed for all indirect
changes in the program flow
RCPU is not serialized (normal mode) and no show cycles will be performed for fetched
instructions
Table A-1. ICTRL Bit Descriptions (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
Description
Table A-2. ISCT_SER Bit Descriptions
0 = Do not ignore first match,
used for “go to x” (reset
value)
1 = Ignore first match (used
for “continue”)
These bits control
serialization and instruction
fetch show cycles. See
Table A-2
definitions.
NOTE: Changing the
instruction show cycle
programming starts to take
effect only from the second
instruction after the actual
mtspr to ICTRL.
Non-compressed mode
Functions Selected
for the bit
Function
0 = Do not ignore first match,
used for “go to x” (reset
value)
1 = Ignore first match (used
for “continue”)
These bits control
serialization and instruction
fetch show cycles. See
Table A-2
definitions.
NOTE: Changing the
instruction show cycle
programming starts to take
effect only from the second
instruction after the actual
mtspr to ICTRL.
Compressed Mode
Freescale Semiconductor
for the bit
1