MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 937

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

23.3.1.1
For protection purposes two possible working modes are defined: debug mode enable and debug mode
disable. These working modes are selected only during reset. See
Debug mode is enabled by asserting DSCK during reset.
Freescale Semiconductor
rfi
Debug Mode Enable
0
. . .
Debug Enable Register
(DER)
.
Debug Mode Enable vs. Debug Mode Disable
. . .
.
. . .
Reset
.
. . .
Set
.
32
MPC561/MPC563 Reference Manual, Rev. 1.2
Q
Figure 23-6. Debug Mode Logic
0
. . .
. . .
Exception Cause Register
(ECR)
.
.
. . .
. . .
Decoder
.
.
. . .
. . .
Internal Debug Mode Signal
.
.
. . .
. . .
.
.
32
Figure 23-7
5
Event valid
Event
for BDM mode selection.
Freeze
ECR_OR
Development Support
23-23