MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 948

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Development Support
The watchpoint trap enables and VSYNC functions are described in section
and Breakpoints
The debug port command function allows the development tool to either assert or negate breakpoint
requests, reset the processor, activate or deactivate the fast down-load procedure.
23.4.6.7
In trap enable mode the only response out of the development port is “sequencing error.”
Data that can come out of the development port is shown in
interrupt” status cannot occur in trap enable mode.
23-34
Start
Start
1
1
Mode
Mode
Table 23-11. Debug Port Command Shifted Into Development Port Shift Register
Serial Data Out of Development Port — Trap Enable Mode
1
1
Table 23-10. Trap Enable Data Shifted into Development Port Shift Register
Support” and section
Contro
Contro
1
l
0
l
1st
Extended
x
0
1
1
x
x
x
0
1
Opcode
- - - - - - Instruction- - - - - -
MPC561/MPC563 Reference Manual, Rev. 1.2
2nd
x
x
0
1
x
0
1
x
x
Section 23.1, “Program Flow
Watchpoint Trap Enables
Major Opcode
00100... 11110
0 = disabled; 1 = enabled
3rd
00000
00001
00010
00011
00011
00011
11111
11111
11111
11111
4th
Table
1st
- - Data- -
Negate Non Maskable breakpoint.
Assert Non Maskable breakpoint.
23-12. “Valid data from CPU” and “CPU
Negate Maskable breakpoint.
Assert Maskable breakpoint.
Start Download procedure
End Download procedure
2nd
Tracking.”
Hard Reset request
Soft Reset request
Reserved
Reserved
Function
VSYNC
NOP
Section 23.2, “Watchpoints
Transfer Data to
Trap Enable
Control Register
Freescale Semiconductor
Function