MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 519

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

When a trigger event causes a CCW execution in progress to be aborted, the aborted conversion is shown
as a ragged end of a shortened CCW rectangle.
The situation diagrams also show when key status bits are set.
Below the queue execution flows are three sets of blocks that show the status information that is made
available to the software. The first two rows of status blocks show the condition of each queue as:
The third row of status blocks shows the 4-bit QS status register field that encodes the condition of the two
queues. Two transition status cases, QS = 0011 and QS = 0111, are not shown because they exist only very
briefly between stable status conditions.
The first three examples in
a new trigger event is recognized before the queue has completed servicing the previous trigger event on
the same queue.
In situation S1
working on the previously recognized trigger event. The trigger overrun error status bit is set, and
otherwise, the premature trigger event is ignored. A trigger event that occurs before the servicing of the
previous trigger event is completed does not disturb the queue execution in progress.
Freescale Semiconductor
•
•
•
•
•
Trigger Overrun
Idle
Active
Pause
Suspended (queue 2 only)
Trigger pending
Error (TOR)
CF Flag
PF Flag
Bit
(Figure
13-27), one trigger event is being recognized on each queue while that queue is still
Set when the end of the queue is reached
Set when a queue completes execution up through a pause bit
Set when a new trigger event occurs before the queue is finished serving the previous trigger
event
Figure 13-27
MPC561/MPC563 Reference Manual, Rev. 1.2
through
Table 13-23. Status Bits
Figure 13-29
Function
(S1, S2, and S3) show what happens when
Table 13-23
describes the status bits.
QADC64E Legacy Mode Operation
13-55