MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 754

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Modular Input/Output Subsystem (MIOS14)
17.8.4
When the RESET signal is asserted, only the FREN, EDGP, EDGN, and CLS bits in the MMCSMSCR are
cleared. The clock prescaler CP, PINC, and PINL bits in the same register are not cleared.
The MMCSMCNT and the MMCSMML, together with the clock prescaler register bits, must be initialized
by software, because they are undefined after a hardware reset. A modulus value must be written to the
MMCSMCNT (which also writes into the MMCSMML) before the MMCSMSCR is written to. The latter
access initializes the clock prescaler.
17.8.5
The privilege level to access to the MMCSM registers depends on the MIOS14MCR SUPV bit. The
privilege level is unrestricted after SRESET and can be changed to supervisor by software.
17.8.5.1
17-22
•
•
The PINC and PINL bits in the MMCSMSCR always reflect the state of the appropriate external
pins.
The MMCSM is disabled after reset and must be explicitly enabled by selecting a clock source
using the CLS bits.
0x30 603A
0x30 603C
0x30 603E
0x30 6030
0x30 6032
0x30 6034
0x30 6036
0x30 6038
0x30 6040
0x30 6042
0x30 6044
0x30 6046
Address
Effect of RESET on MMCSM
MMCSM Registers
MMCSM Register Organization
MMCSM6 Up-Counter Register (MMCSMCNT)
See
MMCSM6 Modulus Latch Register (MMCSMML)
See
MMCSM6 Status/Control Register Duplicated (MMCSMSCRD)
See
MMCSM6 Status/Control Register (MMCSMSCR).
See
MMCSM7 Up-Counter Register (MMCSMCNT)
MMCSM7 Modulus Latch Register (MMCSMML)
MMCSM7 Status/Control Register Duplicated (MMCSMSCRD)
MMCSM7 Status/Control Register (MMCSMSCR)
MMCSM8 Up-Counter Register (MMCSMCNT)
MMCSM8 Modulus Latch Register (MMCSMML)
MMCSM8 Status/Control Register Duplicated (MMCSMSCRD)
MMCSM8 Status/Control Register (MMCSMSCR)
Table 17-10
Table 17-11
Section 17.8.5.5, “MMCSM Status/Control Register
Table 17-12
MPC561/MPC563 Reference Manual, Rev. 1.2
for bit descriptions.
for bit descriptions.
for bit descriptions.
Table 17-9. MMCSM Address Map
MMCSM6
MMCSM7
MMCSM8
Register
(MMCSMSCR)” for bit descriptions.
Freescale Semiconductor